Chulwoo Kim

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2020
Near threshold voltage digital PLL using low voltage optimised blocks for AR display system
Jun, J., Lee, S. & Kim, C., 2020 Mar 1, In: IET Circuits, Devices and Systems. 14, 2, p. 155-158 4 p.
Research output: Contribution to journal › Review article › peer-review
1 Citation (Scopus)
2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory
Alioto, M., Abadir, M. S., Arslan, T., Boon, C. C., Burg, A., Chang, C. H., Chang, M. F., Chang, Y. W., Chen, P., Corsonello, P., Crovetti, P., Dosho, S., Drechsler, R., Elfadel, I. A. M., Han, R., Hashimoto, M., Heng, C. H., Heo, D., Ho, T. Y. & Homayoun, H. & 37 others, Hwang, Y. S., Joshi, A., Joshi, R. V., Karnik, T., Kim, C., Kim, T. H. T., Kulkarni, J., Kursun, V., Lee, Y., Li, H. H., Li, H., Mishra, P., Mohammad, B., Kermani, M. M., Nagata, M., Nii, K., Pande, P. P., Paul, B. C., Pavlidis, V. F., De Gyvez, J. P., Savidis, I., Schaumont, P., Sebastiano, F., Sengupta, A., Seok, M., Stan, M. R., Tehranipoor, M. M., Todri-Sanial, A., Verhelst, M., Vignoli, V., Wen, X., Xu, J., Zhang, W., Zhang, Z., Zhou, J., Zwolinski, M. & Weber, S., 2019 Feb 1, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27, 2, p. 253-280 28 p., 8629340.
Research output: Contribution to journal › Review article › peer-review

Open Access
6 Citations (Scopus)

Research output