Abstract
A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70p spp , respectively, with a multiplication factor of 1024.
Original language | English |
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Article number | 6380633 |
Pages (from-to) | 2080-2093 |
Number of pages | 14 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 21 |
Issue number | 11 |
DOIs | |
Publication status | Published - 2013 |
Keywords
- All-digital phase-locked loop
- jitter reduction
- pixel clock generation
- time-to-digital converter
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering