10-bit 100-MS/s pipelined ADC using input-swapped opamp sharing and self-calibrated V/I converter

Moo Young Kim; Jinwoo Kim; Tagjong Lee; Chulwoo Kim

doi:10.1109/TVLSI.2010.2050915

10-bit 100-MS/s pipelined ADC using input-swapped opamp sharing and self-calibrated V/I converter

Moo Young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and- distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 ×0.8 mm² of active area.

Original language	English
Article number	5492304
Pages (from-to)	1438-1447
Number of pages	10
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2010.2050915
Publication status	Published - 2011 Aug

Bibliographical note

Funding Information:
Manuscript received November 03, 2009; revised March 08, 2010; accepted May 04, 2010. Date of publication June 28, 2010; date of current version July 27, 2011. This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MEST) (R0A-2007-000-20059-0) and fabricated through the MPW of IC Design Education Center (IDEC) supported by the Korea Ministry of Knowledge Economy (MKE).

Keywords

Opamp-sharing
V/I converter
pipelined analog-to-digital converter (ADC)
self-calibration
switched bias

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2010.2050915

Cite this

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title = "10-bit 100-MS/s pipelined ADC using input-swapped opamp sharing and self-calibrated V/I converter",

abstract = "A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and- distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 ×0.8 mm2 of active area.",

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author = "Kim, {Moo Young} and Jinwoo Kim and Tagjong Lee and Chulwoo Kim",

note = "Funding Information: Manuscript received November 03, 2009; revised March 08, 2010; accepted May 04, 2010. Date of publication June 28, 2010; date of current version July 27, 2011. This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MEST) (R0A-2007-000-20059-0) and fabricated through the MPW of IC Design Education Center (IDEC) supported by the Korea Ministry of Knowledge Economy (MKE).",

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N2 - A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and- distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 ×0.8 mm2 of active area.

AB - A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and- distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 ×0.8 mm2 of active area.

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10-bit 100-MS/s pipelined ADC using input-swapped opamp sharing and self-calibrated V/I converter

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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