10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step

Moo Young Kim; Jinwoo Kim; Tagjong Lee; Chulwoo Kim

doi:10.1109/ASSCC.2008.4708730

10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step

Moo Young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

A 31mW, 10-bit lOOMS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2dB is measured with a 1MHz input frequency. It has been implemented in a 0.18um CMOS process and it occupies 1.6 × 0.8 mm² of active area.

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	65-68
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708730
Publication status	Published - 2008
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 2008 Nov 3 → 2008 Nov 5

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	08/11/3 → 08/11/5

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2008.4708730

Cite this

10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step. / Kim, Moo Young; Kim, Jinwoo; Lee, Tagjong et al.
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 65-68 4708730 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, MY, Kim, J, Lee, T & Kim, C 2008, 10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708730, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 65-68, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 08/11/3. https://doi.org/10.1109/ASSCC.2008.4708730

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title = "10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step",

abstract = "A 31mW, 10-bit lOOMS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2dB is measured with a 1MHz input frequency. It has been implemented in a 0.18um CMOS process and it occupies 1.6 × 0.8 mm2 of active area.",

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N2 - A 31mW, 10-bit lOOMS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2dB is measured with a 1MHz input frequency. It has been implemented in a 0.18um CMOS process and it occupies 1.6 × 0.8 mm2 of active area.

AB - A 31mW, 10-bit lOOMS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2dB is measured with a 1MHz input frequency. It has been implemented in a 0.18um CMOS process and it occupies 1.6 × 0.8 mm2 of active area.

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10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step

Abstract

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