12-Gb/s over four balanced lines utilizing NRZ braid clock signaling with no data overhead and spread transition scheme for 8K UHD intra-panel interfaces

Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang Geun Bae, Jaehun Jun, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines.

Original languageEnglish
Article number8535024
Pages (from-to)463-475
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number2
Publication statusPublished - 2019 Feb

Bibliographical note

Funding Information:
Manuscript received December 29, 2017; revised April 1, 2018, June 8, 2018, August 10, 2018, and October 13, 2018; accepted October 21, 2018. Date of publication November 14, 2018; date of current version January 25, 2019. This paper was approved by Associate Editor Jack Kenney. This work was supported by the National Research Foundation of Korea through the Korea Government within the Ministry of Science, ICT and Future Planning under Grant 2016R1E1A1A02922127. (Corresponding author: Chulwoo Kim.) Y. Lee is with the Department of Semiconductor System Engineering, Korea University, Seoul 02841, South Korea.

Publisher Copyright:
© 2018 IEEE.


  • Braid clock signaling (BCS)
  • clock extraction
  • clock-embedded signaling (CES)
  • electromagnetic interference (EMI)
  • intra-panel interface (IPI)
  • low power
  • receiver margin
  • transceiver
  • transition density (TD)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of '12-Gb/s over four balanced lines utilizing NRZ braid clock signaling with no data overhead and spread transition scheme for 8K UHD intra-panel interfaces'. Together they form a unique fingerprint.

Cite this