12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface

Yeonho Lee; Yoon Jae Choi; Chulwoo Kim

doi:10.1109/ASPDAC.2018.8297323

12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface

Yeonho Lee, Yoon Jae Choi, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a Braid clock signaling scheme with 100% data payload and spread transition scheme. The Braid clock signaling has NRZ signaling margin without any dummy clock bits. Also, this paper describes spread transition schemes for low EMI radiation. The effective data bandwidth is increased by 11.1% with the 500% highly embedded transitions. With a same RX voltage margin, the required power for the termination is 5.4 times smaller than the multi-level signaling.

Original language	English
Title of host publication	ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	287-288
Number of pages	2
Volume	2018-January
ISBN (Electronic)	9781509006021
DOIs	https://doi.org/10.1109/ASPDAC.2018.8297323
Publication status	Published - 2018 Feb 20
Event	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of Duration: 2018 Jan 22 → 2018 Jan 25

Other

Other	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Country/Territory	Korea, Republic of
City	Jeju
Period	18/1/22 → 18/1/25

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ASPDAC.2018.8297323

Cite this

Lee, Y., Choi, Y. J., & Kim, C. (2018). 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (Vol. 2018-January, pp. 287-288). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297323

12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. / Lee, Yeonho; Choi, Yoon Jae; Kim, Chulwoo.
ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 287-288.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, Y, Choi, YJ & Kim, C 2018, 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. in ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 287-288, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 18/1/22. https://doi.org/10.1109/ASPDAC.2018.8297323

Lee Y, Choi YJ, Kim C. 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 287-288 doi: 10.1109/ASPDAC.2018.8297323

Lee, Yeonho ; Choi, Yoon Jae ; Kim, Chulwoo. / 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 287-288

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12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface

Abstract

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ASJC Scopus subject areas

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