2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter

Dae Yong Kim; Gil Su Kim; Hoon Jae Ki; Soo Won Kim

2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter

Dae Yong Kim, Gil Su Kim, Hoon Jae Ki, Soo Won Kim

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW from 2.5V supply voltage. This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

Original language	English
Publication status	Published - 2003 Jan 1
Event	8th International Workshop on ADC Modelling and Testing, IWADC 2003 - Perugia, Italy Duration: 2003 Sept 8 → 2003 Sept 10

Conference

Conference	8th International Workshop on ADC Modelling and Testing, IWADC 2003
Country/Territory	Italy
City	Perugia
Period	03/9/8 → 03/9/10

Keywords

1.5bit per stage
Analog-to-digital converter
MDAC
Pipeline ADC
Switched-capacitor circuits

ASJC Scopus subject areas

Modelling and Simulation

Cite this

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title = "2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter",

abstract = "In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW from 2.5V supply voltage. This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.",

keywords = "1.5bit per stage, Analog-to-digital converter, MDAC, Pipeline ADC, Switched-capacitor circuits",

author = "Kim, {Dae Yong} and Kim, {Gil Su} and Ki, {Hoon Jae} and Kim, {Soo Won}",

year = "2003",

month = jan,

day = "1",

language = "English",

note = "8th International Workshop on ADC Modelling and Testing, IWADC 2003 ; Conference date: 08-09-2003 Through 10-09-2003",

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TY - CONF

T1 - 2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter

AU - Kim, Dae Yong

AU - Kim, Gil Su

AU - Ki, Hoon Jae

AU - Kim, Soo Won

PY - 2003/1/1

Y1 - 2003/1/1

N2 - In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW from 2.5V supply voltage. This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

AB - In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW from 2.5V supply voltage. This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

KW - 1.5bit per stage

KW - Analog-to-digital converter

KW - MDAC

KW - Pipeline ADC

KW - Switched-capacitor circuits

UR - http://www.scopus.com/inward/record.url?scp=85073293946&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85073293946&partnerID=8YFLogxK

M3 - Paper

T2 - 8th International Workshop on ADC Modelling and Testing, IWADC 2003

Y2 - 8 September 2003 through 10 September 2003

ER -

2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter

Abstract

Conference

Keywords

ASJC Scopus subject areas

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