TY - JOUR
T1 - 3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop
AU - Bae, Sang Geun
AU - Kim, Yongtae
AU - Park, Yunsoo
AU - Kim, Chulwoo
N1 - Funding Information:
This work was supported by the National Research Foundation of Korea through the Korean Government within the Ministry of Science, ICT and Future Planning under Grant 2016R1E1A1A02922127.
Publisher Copyright:
© 2016 IEEE.
PY - 2017/2
Y1 - 2017/2
N2 - True random number generators (TRNGs) are important in data encryption for information security applications. In this paper, we propose a TRNG that utilizes a comparator in the common-mode operation and the sampling uncertainty of a D flip-flop (DFF). The comparator output is affected by the input common-mode noise and the noise that is simultaneously self-induced. A slicer generates an unpredictable and asynchronous pulse to the input of the DFF according to the output-referred noise of the comparator. By sampling the random pulse with a 3-GHz external clock, there is a sampling uncertainty, which helps to increase the random quality. As a result, we use the independent two random sources for TRNG. The area of the designed circuit is 1609 μm2. In spite of the small size, the data rate of the proposed TRNG is 3 Gb/s. We verify that the output bit stream passes all of the National Institute of Standards and Technology test suites. We fabricate the TRNG in a 65-nm CMOS process with a 1.2 V supply voltage. The power consumption of the proposed TRNG is 5 mW, and the energy per bit is 1.6 pJ/b.
AB - True random number generators (TRNGs) are important in data encryption for information security applications. In this paper, we propose a TRNG that utilizes a comparator in the common-mode operation and the sampling uncertainty of a D flip-flop (DFF). The comparator output is affected by the input common-mode noise and the noise that is simultaneously self-induced. A slicer generates an unpredictable and asynchronous pulse to the input of the DFF according to the output-referred noise of the comparator. By sampling the random pulse with a 3-GHz external clock, there is a sampling uncertainty, which helps to increase the random quality. As a result, we use the independent two random sources for TRNG. The area of the designed circuit is 1609 μm2. In spite of the small size, the data rate of the proposed TRNG is 3 Gb/s. We verify that the output bit stream passes all of the National Institute of Standards and Technology test suites. We fabricate the TRNG in a 65-nm CMOS process with a 1.2 V supply voltage. The power consumption of the proposed TRNG is 5 mW, and the energy per bit is 1.6 pJ/b.
KW - Data encryption
KW - National Institute of Standards and Technology (NIST) test
KW - true random number generator (TRNG)
UR - http://www.scopus.com/inward/record.url?scp=84997673971&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2016.2625341
DO - 10.1109/JSSC.2016.2625341
M3 - Article
AN - SCOPUS:84997673971
SN - 0018-9200
VL - 52
SP - 605
EP - 610
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
M1 - 7756633
ER -