TY - JOUR
T1 - 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
AU - Park, Hyunsu
AU - Song, Junyoung
AU - Sim, Jincheol
AU - Choi, Yoonjae
AU - Choi, Jonghyuck
AU - Yoo, Jeongsik
AU - Kim, Chulwoo
N1 - Funding Information:
Manuscript received February 19, 2020; revised May 11, 2020; accepted June 28, 2020. Date of publication July 15, 2020; date of current version January 28, 2021. This article was approved by Guest Editor Jonathan Chang. This work was supported by the Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant funded by the Korean Government (MSIT) (Development of LPDDR5 Memory Interface for A.I Application Processor) under Grant 2019-0-01370. (Corresponding author: Chulwoo Kim.) Hyunsu Park is with the Department of Semiconductor System Engineering, Korea University, Seoul 02841, South Korea.
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2021/2
Y1 - 2021/2
N2 - A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin bit efficiency is achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 data using a low-power encoding logic and an output driver. The receiver achieves a bit error rate (BER) of less than 1E-12 over an 80-mm FR-4 printed circuit board (PCB) channel. At the maximum data rate, the bit efficiency of the transceiver is 1.11 pJ/bit, consuming 33.4 mW. In the receiver, the attenuated PAM-3 data are equalized by a continuous-time linear equalizer (CTLE) and a one-tap tri-level DFE, which has the same complexity as that of non-return-to-zero (NRZ) signaling. The tri-state buffers, which have a floating PMOS switch, convert the output of the comparator into NRZ data, resulting in reduced delay and power dissipation. Four channels of the transceivers operate at data rates of up to 30 × 4 Gb/s, and the horizontal eye margin of the measured PAM-3 data is achieved at a UI of 0.14 for the PRBS-7 pattern at the maximum data rate.
AB - A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin bit efficiency is achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 data using a low-power encoding logic and an output driver. The receiver achieves a bit error rate (BER) of less than 1E-12 over an 80-mm FR-4 printed circuit board (PCB) channel. At the maximum data rate, the bit efficiency of the transceiver is 1.11 pJ/bit, consuming 33.4 mW. In the receiver, the attenuated PAM-3 data are equalized by a continuous-time linear equalizer (CTLE) and a one-tap tri-level DFE, which has the same complexity as that of non-return-to-zero (NRZ) signaling. The tri-state buffers, which have a floating PMOS switch, convert the output of the comparator into NRZ data, resulting in reduced delay and power dissipation. Four channels of the transceivers operate at data rates of up to 30 × 4 Gb/s, and the horizontal eye margin of the measured PAM-3 data is achieved at a UI of 0.14 for the PRBS-7 pattern at the maximum data rate.
KW - Decision feedback equalizer (DFE)
KW - double data rate (DDR)
KW - high-speed memory interface
KW - pulse amplitude modulation (PAM-3)
KW - single-ended interface
UR - http://www.scopus.com/inward/record.url?scp=85100295898&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2020.3006864
DO - 10.1109/JSSC.2020.3006864
M3 - Article
AN - SCOPUS:85100295898
SN - 0018-9200
VL - 56
SP - 581
EP - 590
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
M1 - 9141289
ER -