Abstract
We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high fMAX (338 GHz) and a low fT (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) fT and fMAX, a simple figure of merit proportional to √fT/RBCCB with RB and CCB extracted from S-parameter measurement is best correlated to the minimum gate delay.
Original language | English |
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Pages (from-to) | 324-326 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 24 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2003 May |
Externally published | Yes |
Keywords
- Germanium
- HBTs
- High-speed devices
- Ring oscillators
- SiGe
- Silicon
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering