Abstract
We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high fMAX (338 GHz) and a low fT (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) fT and fMAX, a simple figure of merit proportional to √fT/RBCCB with RB and CCB extracted from S-parameter measurement is best correlated to the minimum gate delay.
Original language | English |
---|---|
Pages (from-to) | 324-326 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 24 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2003 May |
Externally published | Yes |
Bibliographical note
Funding Information:Manuscript received February 20, 2003; revised March 13, 2003. This work was supported in part by DARPA Contract N66001–02-C-8014. The review of this letter was arranged by Editor K. De Meyer B. Jagannathan, J.-S. Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna and G. Freeman are with the IBM Microelectronics Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 USA (e-mail: [email protected]).
Keywords
- Germanium
- HBTs
- High-speed devices
- Ring oscillators
- SiGe
- Silicon
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering