3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

Basanth Jagannathan; Mounir Meghelli; Kevin Chan; Jae Sung Rieh; Kathryn Schonenberg; David Ahlgren; Seshadri Subbanna; Greg Freeman

doi:10.1109/LED.2003.812568

3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

Basanth Jagannathan, Mounir Meghelli, Kevin Chan, Jae Sung Rieh, Kathryn Schonenberg, David Ahlgren, Seshadri Subbanna, Greg Freeman

Research output: Contribution to journal › Article › peer-review

37 Citations (Scopus)

Abstract

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f_MAX (338 GHz) and a low f_T (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f_T and f_MAX, a simple figure of merit proportional to √f_T/R_BC_CB with R_B and C_CB extracted from S-parameter measurement is best correlated to the minimum gate delay.

Original language	English
Pages (from-to)	324-326
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	24
Issue number	5
DOIs	https://doi.org/10.1109/LED.2003.812568
Publication status	Published - 2003 May
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received February 20, 2003; revised March 13, 2003. This work was supported in part by DARPA Contract N66001–02-C-8014. The review of this letter was arranged by Editor K. De Meyer B. Jagannathan, J.-S. Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna and G. Freeman are with the IBM Microelectronics Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 USA (e-mail: [email protected]).

Keywords

Germanium
HBTs
High-speed devices
Ring oscillators
SiGe
Silicon

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2003.812568

Cite this

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title = "3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay",

abstract = "We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high fMAX (338 GHz) and a low fT (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) fT and fMAX, a simple figure of merit proportional to √fT/RBCCB with RB and CCB extracted from S-parameter measurement is best correlated to the minimum gate delay.",

keywords = "Germanium, HBTs, High-speed devices, Ring oscillators, SiGe, Silicon",

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note = "Funding Information: Manuscript received February 20, 2003; revised March 13, 2003. This work was supported in part by DARPA Contract N66001–02-C-8014. The review of this letter was arranged by Editor K. De Meyer B. Jagannathan, J.-S. Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna and G. Freeman are with the IBM Microelectronics Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 USA (e-mail: [email protected]).",

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AU - Jagannathan, Basanth

AU - Meghelli, Mounir

AU - Chan, Kevin

AU - Rieh, Jae Sung

AU - Schonenberg, Kathryn

AU - Ahlgren, David

AU - Subbanna, Seshadri

AU - Freeman, Greg

N1 - Funding Information: Manuscript received February 20, 2003; revised March 13, 2003. This work was supported in part by DARPA Contract N66001–02-C-8014. The review of this letter was arranged by Editor K. De Meyer B. Jagannathan, J.-S. Rieh, K. Schonenberg, D. Ahlgren, S. Subbanna and G. Freeman are with the IBM Microelectronics Semiconductor Research and Development Center (SRDC), Hopewell Junction, NY 12533 USA (e-mail: [email protected]).

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AB - We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high fMAX (338 GHz) and a low fT (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) fT and fMAX, a simple figure of merit proportional to √fT/RBCCB with RB and CCB extracted from S-parameter measurement is best correlated to the minimum gate delay.

KW - Germanium

KW - HBTs

KW - High-speed devices

KW - Ring oscillators

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3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

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Keywords

ASJC Scopus subject areas

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