6.4: A Clock-embedded Voltage Differential Signaling (CVDS) for the chip-on-glass application of TFT-LCD

Hyun Kyu Jeonk; Yong Hwan Moon; Jeong Il Seo; Ju Pyo Hong; Kwang Il Oh; Jun Ho Kim; Jung Hwan Choi; Seok Jae Park; Joon Ho Na; Jae Ryun Shim; Heong Seog Oh; Dae Seong Kim; Dae Keun Han; Jeong Ho Kang; Koo Won Kang; Kyoung Tae Moon; Jin Kyu Kim; Hyun Chul Choi; Lee Sup Kim

doi:10.1889/1.3500556

6.4: A Clock-embedded Voltage Differential Signaling (CVDS) for the chip-on-glass application of TFT-LCD

Hyun Kyu Jeonk, Yong Hwan Moon, Jeong Il Seo, Ju Pyo Hong, Kwang Il Oh, Jun Ho Kim, Jung Hwan Choi, Seok Jae Park, Joon Ho Na, Jae Ryun Shim, Heong Seog Oh, Dae Seong Kim, Dae Keun Han, Jeong Ho Kang, Koo Won Kang, Kyoung Tae Moon, Jin Kyu Kim, Hyun Chul Choi, Lee Sup Kim

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

An intra-panel interface for the Chip-On-Glass (COG) application is developed using a Clock-embedded Voltage Differential Signaling (CVDS). The proposed interface adopts an embedded clock scheme to eliminate the skew between data and clock signals. The transmitter and receiver for the proposed interface are equipped with the transition compensator and equalizer to overcome the frequency limitation caused by highly resistive Line-On-Glass (LOG) of the COG application. The maximum data rate per pair is measured as high as 780Mbps at the prototype with the refresh rate up to 105Hz. The proposed interface achieves low electromagnetic interference (EMI) and low power consumption. The power consumption of the proposed interface is reduced by 50% compared to the conventional interfaces for the COG application.

Original language	English
Pages (from-to)	66-69
Number of pages	4
Journal	Digest of Technical Papers - SID International Symposium
Volume	41 1
DOIs	https://doi.org/10.1889/1.3500556
Publication status	Published - 2010 May
Externally published	Yes

ASJC Scopus subject areas

General Engineering

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Jeonk, H. K., Moon, Y. H., Seo, J. I., Hong, J. P., Oh, K. I., Kim, J. H., Choi, J. H., Park, S. J., Na, J. H., Shim, J. R., Oh, H. S., Kim, D. S., Han, D. K., Kang, J. H., Kang, K. W., Moon, K. T., Kim, J. K., Choi, H. C., & Kim, L. S. (2010). 6.4: A Clock-embedded Voltage Differential Signaling (CVDS) for the chip-on-glass application of TFT-LCD. Digest of Technical Papers - SID International Symposium, 41 1, 66-69. https://doi.org/10.1889/1.3500556

Jeonk, HK, Moon, YH, Seo, JI, Hong, JP, Oh, KI, Kim, JH, Choi, JH, Park, SJ, Na, JH, Shim, JR, Oh, HS, Kim, DS, Han, DK, Kang, JH, Kang, KW, Moon, KT, Kim, JK, Choi, HC & Kim, LS 2010, '6.4: A Clock-embedded Voltage Differential Signaling (CVDS) for the chip-on-glass application of TFT-LCD', Digest of Technical Papers - SID International Symposium, vol. 41 1, pp. 66-69. https://doi.org/10.1889/1.3500556

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title = "6.4: A Clock-embedded Voltage Differential Signaling (CVDS) for the chip-on-glass application of TFT-LCD",

abstract = "An intra-panel interface for the Chip-On-Glass (COG) application is developed using a Clock-embedded Voltage Differential Signaling (CVDS). The proposed interface adopts an embedded clock scheme to eliminate the skew between data and clock signals. The transmitter and receiver for the proposed interface are equipped with the transition compensator and equalizer to overcome the frequency limitation caused by highly resistive Line-On-Glass (LOG) of the COG application. The maximum data rate per pair is measured as high as 780Mbps at the prototype with the refresh rate up to 105Hz. The proposed interface achieves low electromagnetic interference (EMI) and low power consumption. The power consumption of the proposed interface is reduced by 50% compared to the conventional interfaces for the COG application.",

author = "Jeonk, {Hyun Kyu} and Moon, {Yong Hwan} and Seo, {Jeong Il} and Hong, {Ju Pyo} and Oh, {Kwang Il} and Kim, {Jun Ho} and Choi, {Jung Hwan} and Park, {Seok Jae} and Na, {Joon Ho} and Shim, {Jae Ryun} and Oh, {Heong Seog} and Kim, {Dae Seong} and Han, {Dae Keun} and Kang, {Jeong Ho} and Kang, {Koo Won} and Moon, {Kyoung Tae} and Kim, {Jin Kyu} and Choi, {Hyun Chul} and Kim, {Lee Sup}",

year = "2010",

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doi = "10.1889/1.3500556",

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AU - Seo, Jeong Il

AU - Hong, Ju Pyo

AU - Oh, Kwang Il

AU - Kim, Jun Ho

AU - Choi, Jung Hwan

AU - Park, Seok Jae

AU - Na, Joon Ho

AU - Shim, Jae Ryun

AU - Oh, Heong Seog

AU - Kim, Dae Seong

AU - Han, Dae Keun

AU - Kang, Jeong Ho

AU - Kang, Koo Won

AU - Moon, Kyoung Tae

AU - Kim, Jin Kyu

AU - Choi, Hyun Chul

AU - Kim, Lee Sup

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AB - An intra-panel interface for the Chip-On-Glass (COG) application is developed using a Clock-embedded Voltage Differential Signaling (CVDS). The proposed interface adopts an embedded clock scheme to eliminate the skew between data and clock signals. The transmitter and receiver for the proposed interface are equipped with the transition compensator and equalizer to overcome the frequency limitation caused by highly resistive Line-On-Glass (LOG) of the COG application. The maximum data rate per pair is measured as high as 780Mbps at the prototype with the refresh rate up to 105Hz. The proposed interface achieves low electromagnetic interference (EMI) and low power consumption. The power consumption of the proposed interface is reduced by 50% compared to the conventional interfaces for the COG application.

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6.4: A Clock-embedded Voltage Differential Signaling (CVDS) for the chip-on-glass application of TFT-LCD

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