8 mw1.65-gbps continuous-time equalizer with clock attenuation detection for digital display interface

Kyu Young Kim, Woo Kwan Lee, Jae Tack Yoo, Soo Won Kim

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a continuous-time equalizer which provides a low-power, small area and low-cost solution for a DDI implementation. Proposed equalizer adopts clock attenuation detector, enabling one to eliminate complexand-large feed-back loops, and to achieve compact design and low-power consumption. Using the attenuation signal to all four adaptive equalizer filters composed of three signal channels and a clock channel, one curtails three adaptive attenuation detectors in a multi-channel DDI. The design was done in 0.18-lm CMOS technology. Experimental results summarize that this equalizer can compensate up to-33 dB channel attenuation at 1.65-Gbps DDI rate, showing eye-width of 0.70 UI. Its average power consumption is 8 mW and the effective area is 0.127 mm2. This power consumption is very low in comparison to those of previous researches and the effective area is very small.

Original languageEnglish
Pages (from-to)329-337
Number of pages9
JournalAnalog Integrated Circuits and Signal Processing
Volume63
Issue number2
DOIs
Publication statusPublished - 2010 May

Bibliographical note

Funding Information:
Acknowledgments This work was supported by ‘‘System IC 2010’’ project of Korea Ministry of Commerce, Industry and Energy and by Nano IP/SoC Promotion Group of Seoul R&BD Program (10560). And the authors would like to thank IC Design Education Center (IDEC) and the Korea Ministry of Knowledge Economy (MKE) for the fabrication of the chip.

Keywords

  • Attenuation detection
  • Continuous-time equalizer
  • D flip-flop
  • Digital display interface
  • Equalizer filter

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films

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