8.9 A 96.5% Peak Efficiency Duty-Independent DC-DC Step-Up Converter with Low Input-Level Voltage Stress and Mode-Adaptive Inductor Current Reduction

Minsu Kim, Woojoong Jung, Hyunjun Park, Junho Song, Youngkook Ahn, Taekyu Nam, Yoonsoo Shin, Young Jin Woo, Hyung Min Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DC-DC step-up converters have been widely utilized to efficiently convert a low input voltage (VIN) to a higher output voltage (VOUT) in USB- or battery-powered mobile systems, including battery chargers (10 to 13V), OLED drivers (5 to 13V), etc. The conventional boost converter (CBC) needs the use of high-voltage (HV) devices such as LDMOS to withstand its high VOUT. Typically, HV devices have larger active area and parasitic capacitance compared to low-voltage (LV) devices with the same on-resistance (RON), resulting in the increase of switching loss (i.e., lower switching performance). Moreover, as the duty (D) increases for higher VOUT in a fixed conversion ratio (CR=VOUT/VIN), the inductor current (IL) also increases in proportion to 1/(1-D) times of the load current (ILOAD). Since a large-sized inductor with low parasitic DC resistance (DCR) is challenging to use in mobile devices due to space and cost constraints, larger IL causes significant conduction loss (Pcd,loss) due to DCR and limits the power efficiency in CBC [1]. To mitigate the effect of DCR in the inductor, prior works have used an additional inductor or capacitor as shown in Fig. 8.9.1 (top). A dual-path step-up converter in [2] reduces IL with an LC dual-path technique, which transfers the current to the output through C-path in addition to L-path, but the maximum voltage stress (MVS) across the switches is high as 2VOUT -VIN, requiring 8V LDMOS transistors to operate with 2V input and 5V output voltages. A hybrid converter described in [3] utilizes two inductors and one capacitor for continuous current delivery to the output, reducing the current flowing through each inductor. However, the sum of two inductor currents is still high as ILOAD/(1-D) while HV LDMOS transistors are also required since MVS across the switches is high as VOUT. Another approach to decrease MVS of switches is using a 3-level boost converter in which the voltage stress across switches can be a half of VOUT thanks to its stacked topology. However, HV LDMOS should be still employed for the output voltage exceeding 10V, and there is no effective solution to reduce IL [4].

Original languageEnglish
Title of host publication2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages160-162
Number of pages3
ISBN (Electronic)9798350306200
DOIs
Publication statusPublished - 2024
Event2024 IEEE International Solid-State Circuits Conference, ISSCC 2024 - San Francisco, United States
Duration: 2024 Feb 182024 Feb 22

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Country/TerritoryUnited States
CitySan Francisco
Period24/2/1824/2/22

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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