A Δ ∑ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

Sang Geun Bae; Sewook Hwang; Junyoung Song; Yeonho Lee; Chulwoo Kim

doi:10.1109/TCSII.2018.2846690

A Δ ∑ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

Sang Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth (^fLBW). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of ^fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest ^fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

Original language	English
Article number	8382229
Pages (from-to)	192-196
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	66
Issue number	2
DOIs	https://doi.org/10.1109/TCSII.2018.2846690
Publication status	Published - 2019 Feb

Keywords

EMI reduction
PLL
SSCG
digital compensation
spread-spectrum clock

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2018.2846690

Cite this

@article{71d59681846b4cbc82f73f566ac366cb,

title = "A Δ ∑ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth",

abstract = "A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth (fLBW). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.",

keywords = "EMI reduction, PLL, SSCG, digital compensation, spread-spectrum clock",

author = "Bae, {Sang Geun} and Sewook Hwang and Junyoung Song and Yeonho Lee and Chulwoo Kim",

note = "Funding Information: Manuscript received March 13, 2018; accepted May 21, 2018. Date of publication June 12, 2018; date of current version January 29, 2019. This work was supported by IT Research and Development Program of MOTIE/KEIT, (Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC) under Grant 10052716. This brief was recommended by Associate Editor G. Kolumban. (Corresponding author: Chulwoo Kim.) S.-G. Bae, S. Hwang, Y. Lee, and C. Kim are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: ckim@korea.ac.kr). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2019",

month = feb,

doi = "10.1109/TCSII.2018.2846690",

language = "English",

volume = "66",

pages = "192--196",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - A Δ ∑ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

AU - Bae, Sang Geun

AU - Hwang, Sewook

AU - Song, Junyoung

AU - Lee, Yeonho

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received March 13, 2018; accepted May 21, 2018. Date of publication June 12, 2018; date of current version January 29, 2019. This work was supported by IT Research and Development Program of MOTIE/KEIT, (Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC) under Grant 10052716. This brief was recommended by Associate Editor G. Kolumban. (Corresponding author: Chulwoo Kim.) S.-G. Bae, S. Hwang, Y. Lee, and C. Kim are with the Department of Electrical Engineering, Korea University, Seoul 136-701, South Korea (e-mail: ckim@korea.ac.kr). Publisher Copyright: © 2004-2012 IEEE.

PY - 2019/2

Y1 - 2019/2

N2 - A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth (fLBW). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

AB - A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth (fLBW). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

KW - EMI reduction

KW - PLL

KW - SSCG

KW - digital compensation

KW - spread-spectrum clock

UR - http://www.scopus.com/inward/record.url?scp=85048552487&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2018.2846690

DO - 10.1109/TCSII.2018.2846690

M3 - Article

AN - SCOPUS:85048552487

SN - 1549-7747

VL - 66

SP - 192

EP - 196

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 2

M1 - 8382229

ER -

A Δ ∑ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this