Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-μm and in a 0.13-μm CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-μm CMOS technology occupies only 0.004 mm2 and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a ± 2% phase error having one-cycle lock time.
|Number of pages
|IEEE Transactions on Circuits and Systems II: Express Briefs
|Published - 2008
Bibliographical noteFunding Information:
Manuscript received April 18, 2007; revised July 24, 2007. This work was supported by the SOC R&D Center of SAMSUNG Electronics Co. and financially supported by the Ministry of Education and Human Resources Development (MOE), the Ministry of Commerce, Industry and Energy (MOCIE), and the Ministry of Labor (MOLAB) through the fostering project of the Lab of Excellency. This paper was recommended by Associate Editor V. Kursun.
- Digital clock generator
- Fast lock time
- Low jitter
- Low power
ASJC Scopus subject areas
- Electrical and Electronic Engineering