A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

Dongsuk Shin; Won Joo Yun; Hyun Woo Lee; Young Jung Choi; Suki Kim; Chulwoo Kim

doi:10.1109/ESSCIRC.2008.4681797

A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

Dongsuk Shin, Won Joo Yun, Hyun Woo Lee, Young Jung Choi, Suki Kim, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

A wide-range low-jitter digital DLL using 0.18um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to Optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170MHz to 1.4GHz. The peak-to-peak jitter is 13.8ps at 1.4GHz and the power consumption is reduced to 27mW.

Original language	English
Title of host publication	ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
Pages	82-85
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2008.4681797
Publication status	Published - 2008
Event	34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom Duration: 2008 Sept 15 → 2008 Sept 19

Publication series

Name	ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Other

Other	34th European Solid-State Circuits Conference, ESSCIRC 2008
Country/Territory	United Kingdom
City	Edinburgh, Scotland
Period	08/9/15 → 08/9/19

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2008.4681797

Cite this

Shin, D., Yun, W. J., Lee, H. W., Choi, Y. J., Kim, S., & Kim, C. (2008). A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. In ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference (pp. 82-85). Article 4681797 (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2008.4681797

A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. / Shin, Dongsuk; Yun, Won Joo; Lee, Hyun Woo et al.
ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 2008. p. 82-85 4681797 (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shin, D, Yun, WJ, Lee, HW, Choi, YJ, Kim, S & Kim, C 2008, A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. in ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference., 4681797, ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, pp. 82-85, 34th European Solid-State Circuits Conference, ESSCIRC 2008, Edinburgh, Scotland, United Kingdom, 08/9/15. https://doi.org/10.1109/ESSCIRC.2008.4681797

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abstract = "A wide-range low-jitter digital DLL using 0.18um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to Optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170MHz to 1.4GHz. The peak-to-peak jitter is 13.8ps at 1.4GHz and the power consumption is reduced to 27mW.",

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AB - A wide-range low-jitter digital DLL using 0.18um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to Optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170MHz to 1.4GHz. The peak-to-peak jitter is 13.8ps at 1.4GHz and the power consumption is reduced to 27mW.

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A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

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