A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications

Young Jae Min; Chan Hui Jeong; Kyu Young Kim; Won Ho Choi; Jong Pil Son; Chulwoo Kim; Soo Won Kim

doi:10.1109/TVLSI.2011.2158011

A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications

Young Jae Min, Chan Hui Jeong, Kyu Young Kim, Won Ho Choi, Jong Pil Son, Chulwoo Kim, Soo Won Kim

Research output: Contribution to journal › Article › peer-review

36 Citations (Scopus)

Abstract

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm ². The measured duty-cycle error for the 50% duty-rate is below ±1% (or ±10 pS) within ±320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

Original language	English
Article number	5930339
Pages (from-to)	1524-1528
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	8
DOIs	https://doi.org/10.1109/TVLSI.2011.2158011
Publication status	Published - 2012

Keywords

DRAM
Double data rate (DDR)
duty-cycle corrector (DCC)
successive approximation register (SAR) controller

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2011.2158011

Cite this

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title = "A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications",

abstract = "This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm 2. The measured duty-cycle error for the 50% duty-rate is below ±1% (or ±10 pS) within ±320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.",

keywords = "DRAM, Double data rate (DDR), duty-cycle corrector (DCC), successive approximation register (SAR) controller",

author = "Min, {Young Jae} and Jeong, {Chan Hui} and Kim, {Kyu Young} and Choi, {Won Ho} and Son, {Jong Pil} and Chulwoo Kim and Kim, {Soo Won}",

note = "Funding Information: Manuscript received December 07, 2010; revised April 21, 2011; accepted May 22, 2011. Date of publication June 27, 2011; date of current version June 14, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MEST) (No.K20902001448-10E0100-03010) and Nano IP/Soc Promotion Group of Seoul R&BD Program (10920).",

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AU - Min, Young Jae

AU - Jeong, Chan Hui

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AU - Choi, Won Ho

AU - Son, Jong Pil

AU - Kim, Chulwoo

AU - Kim, Soo Won

N1 - Funding Information: Manuscript received December 07, 2010; revised April 21, 2011; accepted May 22, 2011. Date of publication June 27, 2011; date of current version June 14, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MEST) (No.K20902001448-10E0100-03010) and Nano IP/Soc Promotion Group of Seoul R&BD Program (10920).

PY - 2012

Y1 - 2012

N2 - This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm 2. The measured duty-cycle error for the 50% duty-rate is below ±1% (or ±10 pS) within ±320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

AB - This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm 2. The measured duty-cycle error for the 50% duty-rate is below ±1% (or ±10 pS) within ±320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

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A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications

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Keywords

ASJC Scopus subject areas

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