A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer

Junseob So; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Hwaseok Shin; Seon Been Lee; Taehwan Kim; Chulwoo Kim

doi:10.1109/ISSCC49661.2025.10904567

A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer

Junseob So
, Youngwook Kwon
, Seungwoo Park
, Seongcheol Kim
, Changmin Sim
, Hwaseok Shin
, Seon Been Lee
, Taehwan Kim
, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

To meet increasing demands for higher throughput from memory interfaces, multi-level signaling techniques such as PAM3 and PAM4 are being increasingly adopted [1-7]. However, the lower SNR due to multi-level signaling necessitates complex equalization, increasing power consumption and area. This paper presents a delay-less capacitivefeedback equalizer (CFE) that performs low-power equalization for PAM4 signaling. The RX, fabricated in a 28nm CMOS technology, achieves an energy efficiency of 0.3pJ/b at 32Gb/s/pin and occupies an active area of 0.00288mm2.

Original language	English
Title of host publication	2025 IEEE International Solid-State Circuits Conference, ISSCC 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331541019
DOIs	https://doi.org/10.1109/ISSCC49661.2025.10904567
Publication status	Published - 2025
Event	72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 - San Francisco, United States Duration: 2025 Feb 16 → 2025 Feb 20

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	72nd IEEE International Solid-State Circuits Conference, ISSCC 2025
Country/Territory	United States
City	San Francisco
Period	25/2/16 → 25/2/20

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC49661.2025.10904567

Cite this

So, J., Kwon, Y., Park, S., Kim, S., Sim, C., Shin, H., Lee, S. B., Kim, T., & Kim, C. (2025). A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. In 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC49661.2025.10904567

A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. / So, Junseob; Kwon, Youngwook; Park, Seungwoo et al.
2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

So, J, Kwon, Y, Park, S, Kim, S, Sim, C, Shin, H, Lee, SB, Kim, T & Kim, C 2025, A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. in 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francisco, United States, 25/2/16. https://doi.org/10.1109/ISSCC49661.2025.10904567

So J, Kwon Y, Park S, Kim S, Sim C, Shin H et al. A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. In 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025. Institute of Electrical and Electronics Engineers Inc. 2025. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC49661.2025.10904567

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abstract = "To meet increasing demands for higher throughput from memory interfaces, multi-level signaling techniques such as PAM3 and PAM4 are being increasingly adopted [1-7]. However, the lower SNR due to multi-level signaling necessitates complex equalization, increasing power consumption and area. This paper presents a delay-less capacitivefeedback equalizer (CFE) that performs low-power equalization for PAM4 signaling. The RX, fabricated in a 28nm CMOS technology, achieves an energy efficiency of 0.3pJ/b at 32Gb/s/pin and occupies an active area of 0.00288mm2.",

author = "Junseob So and Youngwook Kwon and Seungwoo Park and Seongcheol Kim and Changmin Sim and Hwaseok Shin and Lee, \{Seon Been\} and Taehwan Kim and Chulwoo Kim",

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AB - To meet increasing demands for higher throughput from memory interfaces, multi-level signaling techniques such as PAM3 and PAM4 are being increasingly adopted [1-7]. However, the lower SNR due to multi-level signaling necessitates complex equalization, increasing power consumption and area. This paper presents a delay-less capacitivefeedback equalizer (CFE) that performs low-power equalization for PAM4 signaling. The RX, fabricated in a 28nm CMOS technology, achieves an energy efficiency of 0.3pJ/b at 32Gb/s/pin and occupies an active area of 0.00288mm2.

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A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

ASJC Scopus subject areas

Access to Document

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Cite this