A 0.5 v 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique

Jaegeun Song; Jaehun Jun; Jaehun Jun; Chulwoo Kim

doi:10.1109/TCSII.2019.2935168

A 0.5 v 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique

Jaegeun Song, Jaehun Jun, Jaehun Jun, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes 3.09 μW. The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

Original language	English
Article number	8798982
Pages (from-to)	1184-1188
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	67
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2019.2935168
Publication status	Published - 2020 Jul

Bibliographical note

Funding Information:
Manuscript received July 12, 2019; accepted August 11, 2019. Date of publication August 14, 2019; date of current version July 1, 2020. This work was supported by the IT Research and Development Program of MOTIE/KEIT through Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC under Grant 10052716. This brief was recommended by Associate Editor Y. Zhang. (Corresponding author: Chulwoo Kim.) J. Song and C. Kim are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]).

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

SAR ADC
Ultra-low voltage
low power
near-threshold voltage
switching algorithm

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2019.2935168

Cite this

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title = "A 0.5 v 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique",

abstract = "This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes 3.09 μW. The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.",

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note = "Funding Information: Manuscript received July 12, 2019; accepted August 11, 2019. Date of publication August 14, 2019; date of current version July 1, 2020. This work was supported by the IT Research and Development Program of MOTIE/KEIT through Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC under Grant 10052716. This brief was recommended by Associate Editor Y. Zhang. (Corresponding author: Chulwoo Kim.) J. Song and C. Kim are with the Department of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail: [email protected]). Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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N2 - This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes 3.09 μW. The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

AB - This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes 3.09 μW. The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

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A 0.5 v 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

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