A 0.6-V delta-sigma modulator with subthreshold-leakage suppression switches

Hyungdong Roh; Hyoungjoong Kim; Youngkil Choi; Jeongjin Roh; Yi Gyeong Kim; Jong Kee Kwon

doi:10.1109/TCSII.2009.2032444

A 0.6-V delta-sigma modulator with subthreshold-leakage suppression switches

Hyungdong Roh, Hyoungjoong Kim, Youngkil Choi, Jeongjin Roh, Yi Gyeong Kim, Jong Kee Kwon

Research output: Contribution to journal › Article › peer-review

36 Citations (Scopus)

Abstract

A 0.6-V 34-μW delta-sigma modulator implemented by using a standard 0.13-μm complementary metaloxidesemiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order deltasigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 μWfor the modulator, and the core chip size is 0.33 mm².

Original language	English
Article number	5299254
Pages (from-to)	825-829
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	56
Issue number	11
DOIs	https://doi.org/10.1109/TCSII.2009.2032444
Publication status	Published - 2009 Nov

Bibliographical note

Funding Information:
Manuscript received July 16, 2009; revised September 2, 2009. First published October 30, 2009; current version published November 18, 2009. This work was supported by the IT R&D program of MIC/IITA (2008-S-015-01, Development of Analog Circuit Techniques for Mixed SoC based on 45-nm CMOS technology). This paper was recommended by M. Ghovanloo.

Keywords

Analog-to-digital converter (ADC)
Deltasigma modulator
Harmonic distortion
Leakage current
Signal-to-noiseplus-distortion ratio (SNDR)
Switched-capacitor circuit

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2009.2032444

Cite this

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title = "A 0.6-V delta-sigma modulator with subthreshold-leakage suppression switches",

abstract = "A 0.6-V 34-μW delta-sigma modulator implemented by using a standard 0.13-μm complementary metaloxidesemiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order deltasigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 μWfor the modulator, and the core chip size is 0.33 mm2.",

keywords = "Analog-to-digital converter (ADC), Deltasigma modulator, Harmonic distortion, Leakage current, Signal-to-noiseplus-distortion ratio (SNDR), Switched-capacitor circuit",

author = "Hyungdong Roh and Hyoungjoong Kim and Youngkil Choi and Jeongjin Roh and Kim, {Yi Gyeong} and Kwon, {Jong Kee}",

note = "Funding Information: Manuscript received July 16, 2009; revised September 2, 2009. First published October 30, 2009; current version published November 18, 2009. This work was supported by the IT R&D program of MIC/IITA (2008-S-015-01, Development of Analog Circuit Techniques for Mixed SoC based on 45-nm CMOS technology). This paper was recommended by M. Ghovanloo.",

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AU - Kim, Yi Gyeong

AU - Kwon, Jong Kee

N1 - Funding Information: Manuscript received July 16, 2009; revised September 2, 2009. First published October 30, 2009; current version published November 18, 2009. This work was supported by the IT R&D program of MIC/IITA (2008-S-015-01, Development of Analog Circuit Techniques for Mixed SoC based on 45-nm CMOS technology). This paper was recommended by M. Ghovanloo.

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N2 - A 0.6-V 34-μW delta-sigma modulator implemented by using a standard 0.13-μm complementary metaloxidesemiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order deltasigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 μWfor the modulator, and the core chip size is 0.33 mm2.

AB - A 0.6-V 34-μW delta-sigma modulator implemented by using a standard 0.13-μm complementary metaloxidesemiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order deltasigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 μWfor the modulator, and the core chip size is 0.33 mm2.

KW - Analog-to-digital converter (ADC)

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A 0.6-V delta-sigma modulator with subthreshold-leakage suppression switches

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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