A 0.78-0.91-THz wideband frequency tripler is demonstrated using a 250-nm InP DHBT technology. Considering potential inaccuracy of the transistor model at the submillimeter-wave frequencies, a simple one-stage common-emitter topology is adopted for the wideband and stable operation. To enhance the output power and suppress the unwanted harmonics, a harmonic-matched bias network is used for dc feed at the output. The frequency tripler was measured with an on-chip probing method. Although an overmode waveguide probe was used, which imposes an additional measurement loss, a peak output power was measured as -28 dBm at 0.813 THz. The bandwidth for a -35-dBm output power ranges from 0.78 to 0.91 THz. The conversion loss is from 35.9 to 45 dB over the bandwidth. The chip area is 273× 460μm2 and the dc power consumption is 22 mW.
Bibliographical noteFunding Information:
This work was supported by the Ministry of Science and ICT (MSIT), South Korea, under the Information Technology Research Center (ITRC) Support Program supervised by the Institute for Information and Communications Technology Planning and Evaluation (IITP), under Grant IITP-2021-0-01749.
© 2013 IEEE.
- Frequency tripler
- InP DHBT
- WR-10 band
- wideband submillimeter-wave source
ASJC Scopus subject areas
- Computer Science(all)
- Materials Science(all)
- Electrical and Electronic Engineering