A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector

Jincheol Sim; Hyunsu Park; Youngwook Kwon; Seongcheol Kim; Chulwoo Kim

doi:10.1109/ISCAS51556.2021.9401792

A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector

Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401792
Publication status	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 2021 May 22 → 2021 May 28

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	21/5/22 → 21/5/28

Bibliographical note

Publisher Copyright:
© 2021 IEEE

Keywords

Double data rate (DDR)
Duty cycle corrector (DCC)
Duty cycle detector (DCD)
Dynamic random access memory (DRAM)
Memory interface

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS51556.2021.9401792

Cite this

Sim, J., Park, H., Kwon, Y., Kim, S., & Kim, C. (2021). A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401792 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401792

A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector. / Sim, Jincheol; Park, Hyunsu; Kwon, Youngwook et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401792 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sim, J, Park, H, Kwon, Y, Kim, S & Kim, C 2021, A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401792, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 21/5/22. https://doi.org/10.1109/ISCAS51556.2021.9401792

Sim J, Park H, Kwon Y, Kim S, Kim C. A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401792. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS51556.2021.9401792

@inproceedings{4986dd07b6b34ab9ad3dac2540958649,

title = "A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector",

abstract = "Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.",

keywords = "Double data rate (DDR), Duty cycle corrector (DCC), Duty cycle detector (DCD), Dynamic random access memory (DRAM), Memory interface",

author = "Jincheol Sim and Hyunsu Park and Youngwook Kwon and Seongcheol Kim and Chulwoo Kim",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401792",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",

}

TY - GEN

T1 - A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector

AU - Sim, Jincheol

AU - Park, Hyunsu

AU - Kwon, Youngwook

AU - Kim, Seongcheol

AU - Kim, Chulwoo

PY - 2021

Y1 - 2021

N2 - Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

AB - Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

KW - Double data rate (DDR)

KW - Duty cycle corrector (DCC)

KW - Duty cycle detector (DCD)

KW - Dynamic random access memory (DRAM)

KW - Memory interface

UR - http://www.scopus.com/inward/record.url?scp=85109021036&partnerID=8YFLogxK

U2 - 10.1109/ISCAS51556.2021.9401792

DO - 10.1109/ISCAS51556.2021.9401792

M3 - Conference contribution

AN - SCOPUS:85109021036

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

Y2 - 22 May 2021 through 28 May 2021

ER -

A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this