A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion

Hyunchul Park; Kyeongho Lee; Jongsun Park

doi:10.1109/AICAS54282.2022.9870016

A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion

Hyunchul Park, Kyeongho Lee, Jongsun Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a novel 10T SRAM Compute-In-Memory (CIM) architecture that efficiently combines current-domain computation with time-domain analog readout. In the analog multiply and accumulation (MAC) computations of the proposed CIM, by weakening the bit-line (BL) discharge current, the MAC results are linearly formed, thus efficiently processing the binarized inputs and weights. In addition, to reduce the hardware cost of analog readout circuit, a time-domain based analog MAC conversion scheme using the current mirror-based voltage to time converter circuits and the flip-flop based time-to-digital converter (TDC) are employed. The hardware implementation results with 28nm CMOS process technology show that the proposed 128×64 SRAM CIM macro achieves a 1788-TOPS/W with 3.75ns delay at 0.9V. It also shows an 86.01% of inference accuracy using CIFAR-10 dataset with VGG-7 model. Compared with the previous works, the proposed SRAM CIM shows up to 4.43× improvement in TOPS/W.

Original language	English
Title of host publication	Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	455-458
Number of pages	4
ISBN (Electronic)	9781665409964
DOIs	https://doi.org/10.1109/AICAS54282.2022.9870016
Publication status	Published - 2022
Event	4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022 - Incheon, Korea, Republic of Duration: 2022 Jun 13 → 2022 Jun 15

Publication series

Name	Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022

Conference

Conference	4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
Country/Territory	Korea, Republic of
City	Incheon
Period	22/6/13 → 22/6/15

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820), in part by the Institute of Information & communications Technology Planning & evaluation (IITP) grant founded by the Korea government (MIST) (No. 2021-0-00903-002, Development of Physical Vulnerability-based Attacks and its Countermeasures for Reliable On-Device Deep Learning Accelerator Design), and the EDA tool was supported by the IC Design Education Center(IDEC), Korea.

Publisher Copyright:
© 2022 IEEE.

Keywords

compute in memory
current domain compute
memory
time to digital converter

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Computer Vision and Pattern Recognition
Hardware and Architecture
Human-Computer Interaction
Electrical and Electronic Engineering

Access to Document

10.1109/AICAS54282.2022.9870016

Cite this

Park, H., Lee, K., & Park, J. (2022). A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. In Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022 (pp. 455-458). (Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/AICAS54282.2022.9870016

A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. / Park, Hyunchul; Lee, Kyeongho; Park, Jongsun.
Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 455-458 (Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, H, Lee, K & Park, J 2022, A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. in Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022. Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, Institute of Electrical and Electronics Engineers Inc., pp. 455-458, 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, Incheon, Korea, Republic of, 22/6/13. https://doi.org/10.1109/AICAS54282.2022.9870016

Park H, Lee K, Park J. A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. In Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 455-458. (Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022). doi: 10.1109/AICAS54282.2022.9870016

Park, Hyunchul ; Lee, Kyeongho ; Park, Jongsun. / A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 455-458 (Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022).

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abstract = "This paper presents a novel 10T SRAM Compute-In-Memory (CIM) architecture that efficiently combines current-domain computation with time-domain analog readout. In the analog multiply and accumulation (MAC) computations of the proposed CIM, by weakening the bit-line (BL) discharge current, the MAC results are linearly formed, thus efficiently processing the binarized inputs and weights. In addition, to reduce the hardware cost of analog readout circuit, a time-domain based analog MAC conversion scheme using the current mirror-based voltage to time converter circuits and the flip-flop based time-to-digital converter (TDC) are employed. The hardware implementation results with 28nm CMOS process technology show that the proposed 128×64 SRAM CIM macro achieves a 1788-TOPS/W with 3.75ns delay at 0.9V. It also shows an 86.01% of inference accuracy using CIFAR-10 dataset with VGG-7 model. Compared with the previous works, the proposed SRAM CIM shows up to 4.43× improvement in TOPS/W.",

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note = "Funding Information: This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820), in part by the Institute of Information & communications Technology Planning & evaluation (IITP) grant founded by the Korea government (MIST) (No. 2021-0-00903-002, Development of Physical Vulnerability-based Attacks and its Countermeasures for Reliable On-Device Deep Learning Accelerator Design), and the EDA tool was supported by the IC Design Education Center(IDEC), Korea. Publisher Copyright: {\textcopyright} 2022 IEEE.; 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022 ; Conference date: 13-06-2022 Through 15-06-2022",

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N1 - Funding Information: This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820), in part by the Institute of Information & communications Technology Planning & evaluation (IITP) grant founded by the Korea government (MIST) (No. 2021-0-00903-002, Development of Physical Vulnerability-based Attacks and its Countermeasures for Reliable On-Device Deep Learning Accelerator Design), and the EDA tool was supported by the IC Design Education Center(IDEC), Korea. Publisher Copyright: © 2022 IEEE.

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N2 - This paper presents a novel 10T SRAM Compute-In-Memory (CIM) architecture that efficiently combines current-domain computation with time-domain analog readout. In the analog multiply and accumulation (MAC) computations of the proposed CIM, by weakening the bit-line (BL) discharge current, the MAC results are linearly formed, thus efficiently processing the binarized inputs and weights. In addition, to reduce the hardware cost of analog readout circuit, a time-domain based analog MAC conversion scheme using the current mirror-based voltage to time converter circuits and the flip-flop based time-to-digital converter (TDC) are employed. The hardware implementation results with 28nm CMOS process technology show that the proposed 128×64 SRAM CIM macro achieves a 1788-TOPS/W with 3.75ns delay at 0.9V. It also shows an 86.01% of inference accuracy using CIFAR-10 dataset with VGG-7 model. Compared with the previous works, the proposed SRAM CIM shows up to 4.43× improvement in TOPS/W.

AB - This paper presents a novel 10T SRAM Compute-In-Memory (CIM) architecture that efficiently combines current-domain computation with time-domain analog readout. In the analog multiply and accumulation (MAC) computations of the proposed CIM, by weakening the bit-line (BL) discharge current, the MAC results are linearly formed, thus efficiently processing the binarized inputs and weights. In addition, to reduce the hardware cost of analog readout circuit, a time-domain based analog MAC conversion scheme using the current mirror-based voltage to time converter circuits and the flip-flop based time-to-digital converter (TDC) are employed. The hardware implementation results with 28nm CMOS process technology show that the proposed 128×64 SRAM CIM macro achieves a 1788-TOPS/W with 3.75ns delay at 0.9V. It also shows an 86.01% of inference accuracy using CIFAR-10 dataset with VGG-7 model. Compared with the previous works, the proposed SRAM CIM shows up to 4.43× improvement in TOPS/W.

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A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion

Abstract

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Bibliographical note

Keywords

ASJC Scopus subject areas

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