A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling

Jin Han Kim; Young Ho Kwak; Mooyoung Kim; Soo Won Kim; Chulwoo Kim

doi:10.1109/JSSC.2006.880609

A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling

Jin Han Kim, Young Ho Kwak, Mooyoung Kim, Soo Won Kim, Chulwoo Kim

Research output: Contribution to journal › Article › peer-review

53 Citations (Scopus)

Abstract

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm² and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

Original language	English
Article number	1683899
Pages (from-to)	2077-2082
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	41
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2006.880609
Publication status	Published - 2006 Sept

Keywords

Clock generator
DLL-based frequency multiplication
Delay-locked loop (DLL)
Fast lock
Low jitter

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2006.880609

Cite this

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title = "A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling",

abstract = "A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.",

keywords = "Clock generator, DLL-based frequency multiplication, Delay-locked loop (DLL), Fast lock, Low jitter",

author = "Kim, {Jin Han} and Kwak, {Young Ho} and Mooyoung Kim and Kim, {Soo Won} and Chulwoo Kim",

note = "Funding Information: Manuscript received August 24, 2005; revised April 20, 2006. This work was supported by Grant R08-2003-000-10899-0 from the Basic Research Program of the Korea Science and Engineering Foundation and IT-SOC Promotion Group. The authors are with the Department of Electronics Engineering, Korea University, Seoul 136-713, Korea (e-mail:ckim@korea.ac.kr). Digital Object Identifier 10.1109/JSSC.2006.880609",

year = "2006",

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doi = "10.1109/JSSC.2006.880609",

language = "English",

volume = "41",

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AU - Kim, Mooyoung

AU - Kim, Soo Won

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received August 24, 2005; revised April 20, 2006. This work was supported by Grant R08-2003-000-10899-0 from the Basic Research Program of the Korea Science and Engineering Foundation and IT-SOC Promotion Group. The authors are with the Department of Electronics Engineering, Korea University, Seoul 136-713, Korea (e-mail:ckim@korea.ac.kr). Digital Object Identifier 10.1109/JSSC.2006.880609

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N2 - A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

AB - A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

KW - Clock generator

KW - DLL-based frequency multiplication

KW - Delay-locked loop (DLL)

KW - Fast lock

KW - Low jitter

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A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling

Abstract

Keywords

ASJC Scopus subject areas

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