A 1.2GHz delayed clock generator for high-speed microprocessors

Inhwa Jung; Moo Young Kim; Chulwoo Kim

doi:10.1109/ASPDAC.2008.4484068

A 1.2GHz delayed clock generator for high-speed microprocessors

Inhwa Jung, Moo Young Kim, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13um CMOS technology occupies only 0.004mm² and operates at variable input frequencies ranging from 625MHz to 1.2GHz.

Original language	English
Title of host publication	2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages	95-96
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2008.4484068
Publication status	Published - 2008
Event	2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of Duration: 2008 Mar 21 → 2008 Mar 24

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Country/Territory	Korea, Republic of
City	Seoul
Period	08/3/21 → 08/3/24

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2008.4484068

Cite this

A 1.2GHz delayed clock generator for high-speed microprocessors. / Jung, Inhwa; Kim, Moo Young; Kim, Chulwoo.
2008 Asia and South Pacific Design Automation Conference, ASP-DAC. 2008. p. 95-96 4484068 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jung, I, Kim, MY & Kim, C 2008, A 1.2GHz delayed clock generator for high-speed microprocessors. in 2008 Asia and South Pacific Design Automation Conference, ASP-DAC., 4484068, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 95-96, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, Seoul, Korea, Republic of, 08/3/21. https://doi.org/10.1109/ASPDAC.2008.4484068

@inproceedings{a28fe65c950c48dbb97a486227698bcd,

title = "A 1.2GHz delayed clock generator for high-speed microprocessors",

abstract = "A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13um CMOS technology occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz.",

author = "Inhwa Jung and Kim, {Moo Young} and Chulwoo Kim",

year = "2008",

doi = "10.1109/ASPDAC.2008.4484068",

language = "English",

isbn = "9781424419227",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "95--96",

booktitle = "2008 Asia and South Pacific Design Automation Conference, ASP-DAC",

note = "2008 Asia and South Pacific Design Automation Conference, ASP-DAC ; Conference date: 21-03-2008 Through 24-03-2008",

}

TY - GEN

T1 - A 1.2GHz delayed clock generator for high-speed microprocessors

AU - Jung, Inhwa

AU - Kim, Moo Young

AU - Kim, Chulwoo

PY - 2008

Y1 - 2008

N2 - A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13um CMOS technology occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz.

AB - A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13um CMOS technology occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz.

UR - http://www.scopus.com/inward/record.url?scp=49549125612&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2008.4484068

DO - 10.1109/ASPDAC.2008.4484068

M3 - Conference contribution

AN - SCOPUS:49549125612

SN - 9781424419227

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 95

EP - 96

BT - 2008 Asia and South Pacific Design Automation Conference, ASP-DAC

T2 - 2008 Asia and South Pacific Design Automation Conference, ASP-DAC

Y2 - 21 March 2008 through 24 March 2008

ER -

A 1.2GHz delayed clock generator for high-speed microprocessors

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