A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line

Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong Min Kim, Hae Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


A 1.3-4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the delay code sequentially. A bidirectional shift register enables this operation with low power, resulting in bang-bang jitter that is three times smaller than that of a conventional DDLL. Conventional delay control is replaced with sequential delay control after a DDLL lock to reduce the locking time. A DDLL with a wide operation range is achieved with a reconfigurable delay line. Unlike the conventional DDLL, the minimum delay difference is adjustable in the proposed structure. To achieve a wide frequency range, the minimum delay difference of the quadrature clock is increased or decreased in three operation modes. To compensate for local variations in the CMOS process, a skew calibration circuit is implemented with the DDLL. The hardware cost of skew calibration is minimized with the proposed DDLL because it shares the subblocks for sequential delay control. The average phase difference from the quadrature clocks becomes the reference for the 90° phase for skew correction. A duty-cycle corrector (DCC) is implemented by collecting the positive edges of the quadrature-phase clocks. The DDLL consumes 6.5 mW at the maximum clock frequency of 4 GHz. The peak-to-peak jitter is improved from 15.6 to 12.5 ps with sequential delay control.

Original languageEnglish
Article number9312976
Pages (from-to)1886-1896
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number6
Publication statusPublished - 2021 Jun

Bibliographical note

Funding Information:
Manuscript received June 17, 2020; revised November 5, 2020; accepted December 10, 2020. Date of publication January 5, 2021; date of current version May 26, 2021. This article was approved by Guest Editor Daniel Friedman. This work was supported by SK Hynix Inc. (Corresponding author: Chulwoo Kim.) Hyunsu Park and Seungwoo Park are with the Department of Semiconductor System Engineering, Korea University, Seoul 02841, South Korea.

Publisher Copyright:
© 1966-2012 IEEE.


  • Digital delay-locked loop (DDLL)
  • dynamic random access memory (DRAM)
  • memory interface
  • multiphase clock generator
  • quadrature phase clock generator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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