A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm2. The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.
Bibliographical notePublisher Copyright:
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- Digital low-dropout (D-LDO) regulator
- Dynamic voltage frequency scaling (DVFS)
- Fast-transient-response time
- Low-dropout (LDO) regulator
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering