A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

Young Jae Min; Chan Hui Jeong; Junil Moon; Youngsun Han; Soo Won Kim; Chulwoo Kim

doi:10.1587/elex.14.20170461

A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

Young Jae Min, Chan Hui Jeong, Junil Moon, Youngsun Han, Soo Won Kim, Chulwoo Kim

Research output: Contribution to journal › Article › peer-review

Abstract

A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm². The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.

Original language	English
Article number	20170461
Journal	ieice electronics express
Volume	14
Issue number	13
DOIs	https://doi.org/10.1587/elex.14.20170461
Publication status	Published - 2017

Bibliographical note

Publisher Copyright:
© IEICE 2017.

Keywords

Digital low-dropout (D-LDO) regulator
Dynamic voltage frequency scaling (DVFS)
Fast-transient-response time
Low-dropout (LDO) regulator

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1587/elex.14.20170461

Cite this

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title = "A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system",

abstract = "A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm2. The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.",

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AU - Han, Youngsun

AU - Kim, Soo Won

AU - Kim, Chulwoo

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AB - A fast transient-response digital low-dropout regulator (D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm2. The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5 mA to 120 mA, and the step-down time is 0.1 us at 1.2 V of supply voltage. Moreover, the voltage spikes are less than 190 mV.

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A 1.3 V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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