A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays

Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

17 Citations (Scopus)

Abstract

A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-μm CMOS process, is presented. A fast lock time of 7.5 μs and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.

Original languageEnglish
Article number5282592
Pages (from-to)773-777
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume56
Issue number10
DOIs
Publication statusPublished - 2009 Oct 1

Bibliographical note

Funding Information:
Manuscript received March 20, 2009; revised June 21, 2009. Current version published October 16, 2009. This work was supported by the Korea Science and Engineering Foundation (KOSEF) grant funded by the Korea government (MEST) (No. R0A-2007-000-20059-0). The chip fabrication was supported by IC Design Education Center (IDEC) and the Korea Ministry of Knowledge Economy (MKE). This paper was recommended by Associate Editor W. Rhee.

Publisher Copyright:
© 2009 IEEE.

Keywords

  • Clock and data recovery (CDR)
  • Embedded clock
  • Receiver

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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