A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces

Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the present data with previous data. The RX was implemented as half-rate architecture to halve the clock frequency and facilitate the S&H operation. Moreover, the proposed decision feedback equalizer (DFE) is suitable for SR RX and improves the reliability of RX by eliminating inter-symbol interference (ISI). The prototype RX, fabricated using 28-nm CMOS technology, occupies a 0.0016 mm2 active area. The measurement result of the proposed RX achieves a bit-error-rate (BER) under 10-12 with a 15-Gb/s data rate in a 17-inch PCB FR4 channel. The RX consumes 13.56 mW of power and has a power efficiency of 0.90 pJ/bit.

Original languageEnglish
Pages (from-to)101-105
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume70
Issue number1
DOIs
Publication statusPublished - 2023 Jan 1

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (MSIT) under Grant NRF-2020R1A4A1019628.

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • DRAM interface
  • Single-ended receiver
  • decision feedback equalizer
  • self-referenced

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces'. Together they form a unique fingerprint.

Cite this