Abstract
A spread spectrum clock generator is implemented in a 0.18μm CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2dB with 5000ppm down spreading and 27.88pspp of jitter in the SSCG without modulation are measured.
| Original language | English |
|---|---|
| Article number | 4672119 |
| Pages (from-to) | 455-458 |
| Number of pages | 4 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| DOIs | |
| Publication status | Published - 2008 |
| Event | IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: 2008 Sept 21 → 2008 Sept 24 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering