A 1.6 v 1.4 Gbp/s/pin consumer DRAM with self-dynamic voltage scaling technique in 44 nm CMOS technology

  • Hyun Woo Lee*
  • , Ki Han Kim
  • , Young Kyoung Choi
  • , Ju Hwan Sohn
  • , Nak Kyu Park
  • , Kwan Weon Kim
  • , Chulwoo Kim
  • , Young Jung Choi
  • , Byong Tae Chung
    • *Corresponding author for this work

    Research output: Contribution to journal › Article › peer-review

    15 Citations (Scopus)

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    Engineering