A 1.6 v 1.4 Gbp/s/pin consumer DRAM with self-dynamic voltage scaling technique in 44 nm CMOS technology

Keyphrases

• Adaptive Bandwidth 25%
• Adaptive Clock 50%
• Adaptive Design 50%
• Circuitry 25%
• Clock Distribution Network 25%
• Clock Gating 50%
• CMOS Technology 100%
• Data Window 25%
• DDR2 SDRAM 50%
• Delay-locked Loop 25%
• Design Margin 25%
• Design Techniques 50%
• Die Area 25%
• Dynamic Power Consumption 25%
• Dynamic Voltage Scaling 100%
• High Performance 25%
• Operating Frequency 25%
• Operating Process 25%
• Performance Requirements 25%
• Power Supply 25%
• Process Technology 25%
• Process Variation 25%
• Scaling Design 25%
• Scaling Method 25%
• Scaling Technique 100%
• Supply Voltage 75%
• Timing Margin 25%
• Valid Data 25%

Engineering

• Process Variation 25%