Abstract
This paper presents an area- and energy- efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with <10-12 bit-error rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm2 in a 28-nm CMOS technology.
Original language | English |
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Article number | 9521897 |
Pages (from-to) | 118907-118918 |
Number of pages | 12 |
Journal | IEEE Access |
Volume | 9 |
DOIs | |
Publication status | Published - 2021 |
Bibliographical note
Publisher Copyright:© 2013 IEEE.
Keywords
- Adaptive equalizer
- clock and data recovery (CDR)
- continuous-time linear equalizer (CTLE)
- decision feedback equalizer (DFE)
- jitter tolerance
- receiver
- self-error corrector (SEC)
- sub-sampling
ASJC Scopus subject areas
- General Computer Science
- General Materials Science
- General Engineering