@inproceedings{6919eb36b6c64d0ab578a216c4d6c95f,
title = "A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology",
abstract = "DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.",
author = "Lee, {Hyun Woo} and Kim, {Ki Han} and Choi, {Young Kyoung} and Shon, {Ju Hwan} and Park, {Nak Kyu} and Kim, {Kwan Weon} and Chulwoo Kim and Choi, {Young Jung} and Chung, {Byong Tae}",
year = "2011",
doi = "10.1109/ISSCC.2011.5746416",
language = "English",
isbn = "9781612843001",
series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",
pages = "502--503",
booktitle = "2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011",
note = "2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 ; Conference date: 20-02-2011 Through 24-02-2011",
}