A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Hyun Woo Lee; Ki Han Kim; Young Kyoung Choi; Ju Hwan Shon; Nak Kyu Park; Kwan Weon Kim; Chulwoo Kim; Young Jung Choi; Byong Tae Chung

doi:10.1109/ISSCC.2011.5746416

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Hyun Woo Lee, Ki Han Kim, Young Kyoung Choi, Ju Hwan Shon, Nak Kyu Park, Kwan Weon Kim, Chulwoo Kim, Young Jung Choi, Byong Tae Chung

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.

Original language	English
Title of host publication	2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages	502-503
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2011.5746416
Publication status	Published - 2011
Event	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States Duration: 2011 Feb 20 → 2011 Feb 24

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Country/Territory	United States
City	San Francisco, CA
Period	11/2/20 → 11/2/24

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2011.5746416

Cite this

Lee, H. W., Kim, K. H., Choi, Y. K., Shon, J. H., Park, N. K., Kim, K. W., Kim, C., Choi, Y. J., & Chung, B. T. (2011). A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 502-503). [5746416] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2011.5746416

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. / Lee, Hyun Woo; Kim, Ki Han; Choi, Young Kyoung et al.
2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. 2011. p. 502-503 5746416 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, HW, Kim, KH, Choi, YK, Shon, JH, Park, NK, Kim, KW, Kim, C, Choi, YJ & Chung, BT 2011, A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. in 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011., 5746416, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 502-503, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, CA, United States, 11/2/20. https://doi.org/10.1109/ISSCC.2011.5746416

Lee HW, Kim KH, Choi YK, Shon JH, Park NK, Kim KW et al. A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011. 2011. p. 502-503. 5746416. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2011.5746416

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abstract = "DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.",

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AB - DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.

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A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

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