A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process

Young Ho Kwak; Yongtae Kim; Sewook Hwang; Chulwoo Kim

doi:10.1109/TCSI.2012.2215781

A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process

Young Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm² in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 ps_rms and the data eye opening is 0.613UI.

Original language	English
Article number	6419863
Pages (from-to)	303-313
Number of pages	11
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	60
Issue number	2
DOIs	https://doi.org/10.1109/TCSI.2012.2215781
Publication status	Published - 2013

Keywords

65 nm CMOS process
CDR
DLL
PLL
infinite phase shift
oversampling
ping-pong delay line
receiver
voltage regulator
wide tracking range

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TCSI.2012.2215781

Cite this

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abstract = "This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI.",

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AU - Kim, Chulwoo

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AB - This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI.

KW - 65 nm CMOS process

KW - CDR

KW - DLL

KW - PLL

KW - infinite phase shift

KW - oversampling

KW - ping-pong delay line

KW - receiver

KW - voltage regulator

KW - wide tracking range

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A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process

Abstract

Keywords

ASJC Scopus subject areas

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