A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC

Minyoung Song; Inhwa Jung; Sudhakar Pamarti; Chulwoo Kim

doi:10.1109/TCSI.2013.2265975

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC

Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

24 Citations (Scopus)

Abstract

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}² consumes 12 mA and its measured jitter is 4 {\rm ps} _{\rm rms} at 2.4 GHz.

Original language	English
Article number	6585805
Pages (from-to)	3145-3151
Number of pages	7
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	60
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2013.2265975
Publication status	Published - 2013 Dec

Keywords

All-digital PLL (ADPLL)
delay-cell-less TDC
low noise VCO
phase-locked loop (PLL)
time-to-digital converter (TDC)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSI.2013.2265975

Cite this

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abstract = "An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}2 consumes 12 mA and its measured jitter is 4 {\rm ps} \rm rms at 2.4 GHz.",

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A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC

Abstract

Keywords

ASJC Scopus subject areas

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