A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit with Clock Frequency Multiplier

Ja Young Kim; Junyoung Song; Jungtaek You; Sewook Hwang; Sang Geun Bae; Chulwoo Kim

doi:10.1109/TCSII.2015.2503721

A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit with Clock Frequency Multiplier

Ja Young Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang Geun Bae, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm² in a 65-nm CMOS technology.

Original language	English
Pages (from-to)	650-654
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	64
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2015.2503721
Publication status	Published - 2017 Jun

Keywords

Clock and data recovery circuit (CDR)
clock frequency multiplier
referenceless
referenceless frequency acquisition circuit (RFAC)
single loop

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2015.2503721

Cite this

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title = "A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit with Clock Frequency Multiplier",

abstract = "This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.",

keywords = "Clock and data recovery circuit (CDR), clock frequency multiplier, referenceless, referenceless frequency acquisition circuit (RFAC), single loop",

author = "Kim, {Ja Young} and Junyoung Song and Jungtaek You and Sewook Hwang and Bae, {Sang Geun} and Chulwoo Kim",

note = "Funding Information: This work was supported by the National Research Foundation of Korea Grant NRF-2011-0020128 funded by the Ministry of Education, Science and Technology of Korea Government. This paper was recommended by Associate Editor H. Zhang. Publisher Copyright: {\textcopyright} 2016 IEEE.",

year = "2017",

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AU - Kim, Ja Young

AU - Song, Junyoung

AU - You, Jungtaek

AU - Hwang, Sewook

AU - Bae, Sang Geun

AU - Kim, Chulwoo

N1 - Funding Information: This work was supported by the National Research Foundation of Korea Grant NRF-2011-0020128 funded by the Ministry of Education, Science and Technology of Korea Government. This paper was recommended by Associate Editor H. Zhang. Publisher Copyright: © 2016 IEEE.

PY - 2017/6

Y1 - 2017/6

N2 - This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

AB - This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

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KW - referenceless

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A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit with Clock Frequency Multiplier

Abstract

Keywords

ASJC Scopus subject areas

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