A 272–341-GHz Integrated Amplifier-Frequency-Doubler Chain in 65-nm CMOS

Junghwan Yoo, Doyoon Kim, Heekang Son, Wooyong Keum, Sanghyeok Yang, Hyunsoo Kim, Jae Sung Rieh

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


This letter presents the development of a wideband amplifier-frequency-doubler chain (AFDC) operating at around 300 GHz based on a 65-nm CMOS technology. A new output matching technique for the frequency doubler (FD) is proposed, which provides extensively improved bandwidth and output power compared to a conventional approach often used. In addition, a five-stage transformer-based differential power amplifier has been developed that precedes the FD for sufficient input power and improved overall conversion gain. The integrated AFDC exhibited a measured peak output power of −3.0 dBm along with a 3-dB bandwidth of 69 GHz (272–341 GHz) or a fractional bandwidth of 22%. The measured peak conversion gain is 3.8 dB and the power consumption is 159.6 mW. The chip size is 660 × 155 µm excluding probing pads.

Original languageEnglish
Pages (from-to)1215-1218
Number of pages4
JournalIEEE Microwave and Wireless Technology Letters
Issue number8
Publication statusPublished - 2023 Aug 1

Bibliographical note

Publisher Copyright:
© 2023 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.


  • CMOS technology
  • frequency doubler (FD)
  • power amplifier
  • wideband

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics


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