A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.
|Number of pages||9|
|Journal||IEEE Transactions on Terahertz Science and Technology|
|Publication status||Published - 2018 Nov|
Bibliographical noteFunding Information:
Manuscript received March 14, 2018; revised October 6, 2018; accepted October 6, 2018. Date of publication October 12, 2018; date of current version December 11, 2018. This work was supported by a grant to the Terahertz Electronic Device Research Laboratory funded by the Defense Acquisition Program Administration and by the Agency for Defense Development (UD180025RD). (Corresponding author: Jae-Sung Rieh.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,firstname.lastname@example.org; kongbob93@ gmail.com; email@example.com; firstname.lastname@example.org; email@example.com).
© 2011-2012 IEEE.
- CMOS integrated circuits
- frequency synthesizer
- phase-locked loop (PLL)
- ring oscillator
- voltage-controlled oscillator (VCO)
ASJC Scopus subject areas
- Electrical and Electronic Engineering