A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Junghwan Yoo; Doyoon Kim; Jungsoo Kim; Kiryong Song; Jae Sung Rieh

doi:10.1109/TTHZ.2018.2875796

A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Junghwan Yoo, Doyoon Kim, Jungsoo Kim, Kiryong Song, Jae Sung Rieh

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm² excluding probing pads.

Original language	English
Article number	8490719
Pages (from-to)	784-792
Number of pages	9
Journal	IEEE Transactions on Terahertz Science and Technology
Volume	8
Issue number	6
DOIs	https://doi.org/10.1109/TTHZ.2018.2875796
Publication status	Published - 2018 Nov

Bibliographical note

Funding Information:
Manuscript received March 14, 2018; revised October 6, 2018; accepted October 6, 2018. Date of publication October 12, 2018; date of current version December 11, 2018. This work was supported by a grant to the Terahertz Electronic Device Research Laboratory funded by the Defense Acquisition Program Administration and by the Agency for Defense Development (UD180025RD). (Corresponding author: Jae-Sung Rieh.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,zombiend@korea.ac.kr; kongbob93@ gmail.com; kjs132456@gmail.com; acoor@korea.ac.kr; jsrieh@korea.ac.kr).

Publisher Copyright:
© 2011-2012 IEEE.

Keywords

CMOS integrated circuits
frequency synthesizer
phase-locked loop (PLL)
ring oscillator
voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

Radiation
Electrical and Electronic Engineering

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10.1109/TTHZ.2018.2875796

Cite this

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title = "A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS",

abstract = "A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.",

keywords = "CMOS integrated circuits, frequency synthesizer, phase-locked loop (PLL), ring oscillator, voltage-controlled oscillator (VCO)",

author = "Junghwan Yoo and Doyoon Kim and Jungsoo Kim and Kiryong Song and Rieh, {Jae Sung}",

note = "Funding Information: Manuscript received March 14, 2018; revised October 6, 2018; accepted October 6, 2018. Date of publication October 12, 2018; date of current version December 11, 2018. This work was supported by a grant to the Terahertz Electronic Device Research Laboratory funded by the Defense Acquisition Program Administration and by the Agency for Defense Development (UD180025RD). (Corresponding author: Jae-Sung Rieh.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,zombiend@korea.ac.kr; kongbob93@ gmail.com; kjs132456@gmail.com; acoor@korea.ac.kr; jsrieh@korea.ac.kr). Publisher Copyright: {\textcopyright} 2011-2012 IEEE.",

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N1 - Funding Information: Manuscript received March 14, 2018; revised October 6, 2018; accepted October 6, 2018. Date of publication October 12, 2018; date of current version December 11, 2018. This work was supported by a grant to the Terahertz Electronic Device Research Laboratory funded by the Defense Acquisition Program Administration and by the Agency for Defense Development (UD180025RD). (Corresponding author: Jae-Sung Rieh.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,zombiend@korea.ac.kr; kongbob93@ gmail.com; kjs132456@gmail.com; acoor@korea.ac.kr; jsrieh@korea.ac.kr). Publisher Copyright: © 2011-2012 IEEE.

PY - 2018/11

Y1 - 2018/11

N2 - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.

AB - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.

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A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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