A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

Ji Hak Yu; Min Ki Park; Soo-Won Kim

doi:10.1109/ICCE.2016.7430559

A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

Ji Hak Yu, Min Ki Park, Soo-Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

A new time-to-digital converter (TDC) for the time-of-flight measurement (TOF) architecture using a cyclic method and time amplifier (TA) with three level conversions is proposed. To increase the input range of the TDC and protect it from PVT variations, the cyclic method and DLL architecture are used in a second-level conversion. The third conversion calculates the residue remaining after the second conversion as a combination of the Vernier delay line (VDL) and TA in order to implement high resolution. Through the combination of VDL and TA, the area is reduced compared with the single VDL. The proposed TDC has been implemented and simulated in a 65-nm CMOS process with an active core size of um 0.22 mm2. The input range is over 1p, and the minimum time resolution is 2ps with a core power consumption of 69.7 mW.

Original language	English
Title of host publication	2016 IEEE International Conference on Consumer Electronics, ICCE 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	151-152
Number of pages	2
ISBN (Print)	9781467383646
DOIs	https://doi.org/10.1109/ICCE.2016.7430559
Publication status	Published - 2016 Mar 10
Event	IEEE International Conference on Consumer Electronics, ICCE 2016 - Las Vegas, United States Duration: 2016 Jan 7 → 2016 Jan 11

Other

Other	IEEE International Conference on Consumer Electronics, ICCE 2016
Country/Territory	United States
City	Las Vegas
Period	16/1/7 → 16/1/11

Keywords

time amplifier (TA)
time of flight measurement (TOF)
Time-to-digital converter (TDC)

ASJC Scopus subject areas

Computer Networks and Communications
Electrical and Electronic Engineering

Access to Document

10.1109/ICCE.2016.7430559

Cite this

Yu, J. H., Park, M. K., & Kim, S.-W. (2016). A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier. In 2016 IEEE International Conference on Consumer Electronics, ICCE 2016 (pp. 151-152). Article 7430559 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE.2016.7430559

A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier. / Yu, Ji Hak; Park, Min Ki; Kim, Soo-Won.
2016 IEEE International Conference on Consumer Electronics, ICCE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 151-152 7430559.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yu, JH, Park, MK & Kim, S-W 2016, A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier. in 2016 IEEE International Conference on Consumer Electronics, ICCE 2016., 7430559, Institute of Electrical and Electronics Engineers Inc., pp. 151-152, IEEE International Conference on Consumer Electronics, ICCE 2016, Las Vegas, United States, 16/1/7. https://doi.org/10.1109/ICCE.2016.7430559

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abstract = "A new time-to-digital converter (TDC) for the time-of-flight measurement (TOF) architecture using a cyclic method and time amplifier (TA) with three level conversions is proposed. To increase the input range of the TDC and protect it from PVT variations, the cyclic method and DLL architecture are used in a second-level conversion. The third conversion calculates the residue remaining after the second conversion as a combination of the Vernier delay line (VDL) and TA in order to implement high resolution. Through the combination of VDL and TA, the area is reduced compared with the single VDL. The proposed TDC has been implemented and simulated in a 65-nm CMOS process with an active core size of um 0.22 mm2. The input range is over 1p, and the minimum time resolution is 2ps with a core power consumption of 69.7 mW.",

keywords = "time amplifier (TA), time of flight measurement (TOF), Time-to-digital converter (TDC)",

author = "Yu, {Ji Hak} and Park, {Min Ki} and Soo-Won Kim",

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AB - A new time-to-digital converter (TDC) for the time-of-flight measurement (TOF) architecture using a cyclic method and time amplifier (TA) with three level conversions is proposed. To increase the input range of the TDC and protect it from PVT variations, the cyclic method and DLL architecture are used in a second-level conversion. The third conversion calculates the residue remaining after the second conversion as a combination of the Vernier delay line (VDL) and TA in order to implement high resolution. Through the combination of VDL and TA, the area is reduced compared with the single VDL. The proposed TDC has been implemented and simulated in a 65-nm CMOS process with an active core size of um 0.22 mm2. The input range is over 1p, and the minimum time resolution is 2ps with a core power consumption of 69.7 mW.

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A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier

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