A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE

Sewook Hwang; Sungjun Moon; Junyoung Song; Chulwoo Kim

doi:10.1109/VLSIC.2016.7573473

A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE

Sewook Hwang
, Sungjun Moon
, Junyoung Song
, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2-1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER < 10^-12 over a -22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm². The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm².

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Volume	2016-September
ISBN (Electronic)	9781509006342
DOIs	https://doi.org/10.1109/VLSIC.2016.7573473
Publication status	Published - 2016 Sept 21
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 2016 Jun 14 → 2016 Jun 17

Other

Other	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	16/6/14 → 16/6/17

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/VLSIC.2016.7573473

Cite this

A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. / Hwang, Sewook; Moon, Sungjun; Song, Junyoung et al.
2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. Vol. 2016-September Institute of Electrical and Electronics Engineers Inc., 2016. 7573473.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hwang, S, Moon, S, Song, J & Kim, C 2016, A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE. in 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. vol. 2016-September, 7573473, Institute of Electrical and Electronics Engineers Inc., 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 16/6/14. https://doi.org/10.1109/VLSIC.2016.7573473

@inproceedings{ab1b7b5904a84607abf23f6be31f4207,

title = "A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE",

abstract = "This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2-1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER < 10-12 over a -22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm2. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm2.",

author = "Sewook Hwang and Sungjun Moon and Junyoung Song and Chulwoo Kim",

year = "2016",

month = sep,

day = "21",

doi = "10.1109/VLSIC.2016.7573473",

language = "English",

volume = "2016-September",

booktitle = "2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",

}

TY - GEN

T1 - A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE

AU - Hwang, Sewook

AU - Moon, Sungjun

AU - Song, Junyoung

AU - Kim, Chulwoo

PY - 2016/9/21

Y1 - 2016/9/21

N2 - This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2-1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER < 10-12 over a -22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm2. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm2.

AB - This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2-1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER < 10-12 over a -22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm2. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm2.

UR - https://www.scopus.com/pages/publications/84990873257

UR - https://www.scopus.com/pages/publications/84990873257#tab=citedBy

U2 - 10.1109/VLSIC.2016.7573473

DO - 10.1109/VLSIC.2016.7573473

M3 - Conference contribution

AN - SCOPUS:84990873257

VL - 2016-September

BT - 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

Y2 - 14 June 2016 through 17 June 2016

ER -

A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE

Abstract

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