A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver with Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces

Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong Min Kim, Changkyu Choi, Hae Kang Jung, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

A three-level pulse amplitude modulation (PAM-3) transceiver (TRX) with improved simultaneous switching output (SSO) noise and reference voltage margin was studied. PAM- 3 signaling with an insertion of 3 bits in 2-unit intervals (UI) was implemented using the upper, under, and ground voltages, achieving 150% pin efficiency. The ground-referenced signaling (GRS) charge pump driver reduced SSO noise and maintained ground as the solitary return current path. Capacitive peaking and middle edge-rate boosting were implemented for transmitter (TX) equalization. With the receiver (RX), the ground level was used as a reference voltage for a single-to-differential (S2D) amplifier. PAM- 3 signaling was converted to binary data using the time-domain decision technique in comparators. The decision time of comparators for data and reference voltage was compared. This technique shows the increased voltage margin, the reduced decision time, and the decreased error rate. The reduced decision time improved the performance of the PAM- 3 decision feedback equalizer (DFE). A clock disabled the circuit, and a low-power return-to-zero (RZ) to non-RZ (NRZ) converter was configured for the proposed comparator output cases. The prototype TRX was fabricated in a 28-nm complementary metal-oxide silicon (CMOS) process with a surface area of 0.006 mm2. The total power efficiency was recorded as 1.09 pJ/b at 33 Gb/s/pin. Through the flame retardant-4 (FR-4) 20-mm printed circuit board (PCB) channel and coaxial cable, a bit error rate (BER) of 10-12 was measured.

Original languageEnglish
Pages (from-to)2314-2325
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume58
Issue number8
DOIs
Publication statusPublished - 2023 Aug 1

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

  • Decision feedback equalizer (DFE)
  • high-speed memory interface
  • multi-chip module (MCM)
  • pulse amplitude modulation (PAM)-3
  • single-ended interface
  • time-domain decision technique

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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