A 4 × 5-Gb/s 1.12-μs Locking Time Reference-Less Receiver with Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels

A 4 × 5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 ps_rms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.