A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector

Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review


This paper presents a 4-GHz ring-oscillator-based digital sub-sampling phase-locked loop (SSPLL) with an energy-efficient dual-domain phase detector (DDPD). The performance of the digital SSPLL is limited by the quantization noise (Q-noise) of the phase detector (PD), and it requires an analog-to-digital-converter (ADC) and optimally spaced voltage comparators (OSVCs) with a large power and area overhead to reduce the Q-noise. The proposed DDPD efficiently detects a phase error in both the voltage- and time-domains, thereby suppressing the Q-noise while minimizing additional cost. It requires only one comparator in the power-hungry digitally-controlled oscillator (DCO) clock path unlike ADC and OSVCs. Consequently, it achieves a high performance while consuming a small amount of power similar to that of a conventional bang-bang phase detector (BBPD). The proposed SSPLL was implemented in a 28-nm CMOS technology. It consumes 5.35 mW at 4 GHz and occupies an area of 0.014 mm2. The integrated rms jitter is reduced by 25.7% using the proposed DDPD, whereas the overall power dissipation is similar to that of a conventional BBPD-based PLL. The jitter-power FoM1 of the prototype SSPLL is -235.9 dB, and the FoM2 is -250.9 dB.

Original languageEnglish
Pages (from-to)2734-2743
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number7
Publication statusPublished - 2023 Jul 1

Bibliographical note

Funding Information:
This work was supported by the Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant through the Korea Government (MSIT) (A Development of Intelligent PHY Interface for High-Speed PIM Data Transfer) under Grant 2022-0-01171

Publisher Copyright:
© 2004-2012 IEEE.


  • Digital phase-locked loop (PLL)
  • dual-domain phase detector (DDPD)
  • jitter
  • low-power
  • quantization noise (Q-nose)
  • ring oscillator
  • sub-sampling

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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