A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction technique

Junyoung Song; Sewook Hwang; Tae Chan Kim; Chulwoo Kim

doi:10.1007/s10470-014-0258-4

A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction technique

Junyoung Song, Sewook Hwang, Tae Chan Kim, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this Letter, 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 ps_rms at 1.5 GHz operation, and 3.991 ps_rms at 400 MHz operation. The ADPLL occupies 0.088 mm², and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.

Original language	English
Pages (from-to)	183-189
Number of pages	7
Journal	Analog Integrated Circuits and Signal Processing
Volume	79
Issue number	1
DOIs	https://doi.org/10.1007/s10470-014-0258-4
Publication status	Published - 2014 Apr

Bibliographical note

Funding Information:
Acknowledgments This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. 2011-0020128); fabrication was supported by the MPW of IDEC.

Keywords

All-digital PLL
Integer-N PLL
Spur reduction
Wide-range PLL

ASJC Scopus subject areas

Signal Processing
Hardware and Architecture
Surfaces, Coatings and Films

Access to Document

10.1007/s10470-014-0258-4

Cite this

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abstract = "In this Letter, 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 psrms at 1.5 GHz operation, and 3.991 psrms at 400 MHz operation. The ADPLL occupies 0.088 mm2, and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.",

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author = "Junyoung Song and Sewook Hwang and Kim, {Tae Chan} and Chulwoo Kim",

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N1 - Funding Information: Acknowledgments This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. 2011-0020128); fabrication was supported by the MPW of IDEC.

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N2 - In this Letter, 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 psrms at 1.5 GHz operation, and 3.991 psrms at 400 MHz operation. The ADPLL occupies 0.088 mm2, and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.

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A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction technique

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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