TY - JOUR
T1 - A 5-GHz Subsampling PLL-Based Spread-Spectrum Clock Generator by Calibrating the Frequency Deviation
AU - Bae, Sang Geun
AU - Kim, Gyungmin
AU - Kim, Chulwoo
N1 - Funding Information:
Manuscript received May 27, 2016; revised July 18, 2016; accepted November 1, 2016. Date of publication November 3, 2016; date of current version September 25, 2017. This work was supported by the IT Research and Development Program of MOTIE/KEIT (Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC) under Grant 10052716. This brief was recommended by Associate Editor F. Lau.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/10
Y1 - 2017/10
N2 - This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio (δ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a -104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.
AB - This brief presents a spread-spectrum clock generator (SSCG) based on a subsampling phase-locked loop (SSPLL) by calibrating the spreading ratio. The proposed SSCG has a low jitter performance owing to the low in-band phase noise performance of the SSPLL. To achieve a spread-spectrum clocking, the direct voltage-controlled oscillator modulation method is used owing to the absence of a frequency divider. However, the spreading ratio (δ) can be varied by process, voltage, and temperature variations. Automatic calibration technique is proposed for a 5000-ppm spreading ratio at 5 GHz. The proposed SSCG achieves a 21-dB electromagnetic interference reduction, has a -104-dBc/Hz phase noise at 200-kHz offset, and consumes 7 mW and occupies a 0.39-mm2 area in a 65-nm CMOS process.
KW - Auto-calibration
KW - spread-spectrum clock generator (SSCG)
KW - subsampling phase-locked loop (SSPLL)
UR - http://www.scopus.com/inward/record.url?scp=85030871345&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2016.2624759
DO - 10.1109/TCSII.2016.2624759
M3 - Article
AN - SCOPUS:85030871345
SN - 1549-7747
VL - 64
SP - 1132
EP - 1136
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 10
M1 - 7733152
ER -