A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS

Sewook Hwang; Inhwa Jung; Junyoung Song; Chulwoo Kim

doi:10.1109/ISCAS.2012.6271659

A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS

Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

8 Citations (Scopus)

Abstract

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10 ¹² at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm ² using 0.13μm CMOS process.

Original language	English
Pages	1959-1962
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271659
Publication status	Published - 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 2012 May 20 → 2012 May 23

Other

Other	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	12/5/20 → 12/5/23

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISCAS.2012.6271659

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@conference{bd3fc7c6cc17456bbf22d6fa3b0df5b6,

title = "A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS",

abstract = "An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10 12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm 2 using 0.13μm CMOS process.",

author = "Sewook Hwang and Inhwa Jung and Junyoung Song and Chulwoo Kim",

year = "2012",

doi = "10.1109/ISCAS.2012.6271659",

language = "English",

pages = "1959--1962",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS

AU - Hwang, Sewook

AU - Jung, Inhwa

AU - Song, Junyoung

AU - Kim, Chulwoo

PY - 2012

Y1 - 2012

N2 - An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10 12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm 2 using 0.13μm CMOS process.

AB - An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10 12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm 2 using 0.13μm CMOS process.

UR - http://www.scopus.com/inward/record.url?scp=84866612518&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866612518&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271659

DO - 10.1109/ISCAS.2012.6271659

M3 - Paper

AN - SCOPUS:84866612518

SP - 1959

EP - 1962

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13μm CMOS

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