A 6-bit 3.6-GS/s 4-Channel Time-Interleaved ADC With Front-Rank MSB Decision and 2-Then-1.5-bit/Cycle Architecture

This article presents a 6-bit, 3.6-GS/s, 4-channel time-interleaved (TI) analog-to-digital converter (ADC) with a front-rank most significant bit (MSB) decision (FRMD) technique and a 2-then-1.5-bit/cycle successive approximation register (SAR) architecture. The proposed FRMD technique determines the MSB concurrently with sampling, enhancing the conversion speed of the sub-ADCs. The proposed 2-then-1.5-bit/cycle architecture, which aligns well with the FRMD technique, incorporates comparator background offset calibration without consuming extra cycles, zeroing the offset. Since the comparator offset is the dominant source of inter-channel offset mismatch in TI-ADCs, this approach naturally eliminates the need for extra inter-channel offset calibration. A prototype ADC was fabricated in a 28-nm CMOS process, achieving 33.9 dB signal-to-noise-and-distortion ratio (SNDR) and 49.8 dB spurious-free dynamic range (SFDR) at the Nyquist frequency. The ADC consumes 6.15 mW at 3.6 GS/s, resulting in a Walden figure of merit (FoM_W) of 41.8 fJ/conversion-step.