A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge

Kyeongho Lee; Woong Choi; Jongsun Park

doi:10.1109/JSSC.2020.3043186

A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge

Kyeongho Lee, Woong Choi, Jongsun Park

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

This article presents an adaptive match-line (ML) discharge scheme for low-power, high-performance, and compact ternary content addressable memory (TCAM). In the proposed TCAM, the transposed cell topology enables the selectively controlled ML pull-down path and compact array area. By employing the adaptive ML discharge and ML boosting scheme, unnecessary ML discharge and redundant search-line (SL) switching are eliminated for low-cost TCAM search operation. In order to minimize ML voltage swing at a wide voltage range, a timing calibration scheme is also adopted in the proposed TCAM. A 128 $\times $ 64 test chip implemented with 65-nm CMOS technology shows that the proposed adaptive ML discharge improves up to 69% of search delay and saves 37% of search energy compared with the conventional approach at 1.1 V, 100 MHz. The measurement result shows energy efficiency of 0.6 fJ/bit/search and 8% improvement of figure-of-merit (FoM) (energy/bit/search) compared with the state-of-the-art works.

Original language	English
Article number	9307238
Pages (from-to)	2574-2584
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	56
Issue number	8
DOIs	https://doi.org/10.1109/JSSC.2020.3043186
Publication status	Published - 2021 Aug

Bibliographical note

Funding Information:
Manuscript received September 4, 2020; revised November 5, 2020; accepted November 25, 2020. Date of publication December 24, 2020; date of current version July 23, 2021. This article was approved by Associate Editor Vivek De. This work was supported in part by the National Research Foundation of Korea Grant funded by the Korea Government under Grant NRF-2020R1A2C3014820 and Grant NRF-2015M3D1A1070465; in part by Institute for Information & Communications Technology Promotion (IITP) Grant funded by the Korea Government (MSIP) under Grant 2020-0-01077; in part by the Development of Intelligent SoC having Multimodal IOT Interface for Data Sensing, Edge Computing Analysis and Data Sharing; in part by the Next Generation Semiconductor Research and Development Program funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) under Grant 20009972; in part by Sookmyung Women’s University Research Grants under Grant 1-1903-2007; and in part by Samsung Electronics Co., Ltd. (Corresponding author: Woong Choi.) Kyeongho Lee and Jongsun Park are with the School of Electrical Engineering, Korea University, Seoul 136-713, South Korea.

Funding Information:
This work was supported in part by the National Research Foundation of Korea Grant funded by the Korea Government under Grant NRF-2020R1A2C3014820 and Grant NRF-2015M3D1A1070465; in part by Institute for Information & Communications Technology Promotion (IITP) Grant funded by the Korea Government (MSIP) under Grant 2020-0-01077; in part by the Development of Intelligent SoC having Multimodal IOT Interface for Data Sensing, Edge Computing Analysis and Data Sharing; in part by the Next Generation Semiconductor Research and Development Program funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) under Grant 20009972; in part by Sookmyung Women’s University Research Grants under Grant 1-1903-2007; and in part by Samsung Electronics Co., Ltd.

Publisher Copyright:
© 1966-2012 IEEE.

Keywords

Adaptive sensing
content addressable memory (CAM)
memory
reference voltage
sensing margin
ternary CAM (TCAM)

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2020.3043186

Cite this

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title = "A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge",

abstract = "This article presents an adaptive match-line (ML) discharge scheme for low-power, high-performance, and compact ternary content addressable memory (TCAM). In the proposed TCAM, the transposed cell topology enables the selectively controlled ML pull-down path and compact array area. By employing the adaptive ML discharge and ML boosting scheme, unnecessary ML discharge and redundant search-line (SL) switching are eliminated for low-cost TCAM search operation. In order to minimize ML voltage swing at a wide voltage range, a timing calibration scheme is also adopted in the proposed TCAM. A 128 $\times $ 64 test chip implemented with 65-nm CMOS technology shows that the proposed adaptive ML discharge improves up to 69% of search delay and saves 37% of search energy compared with the conventional approach at 1.1 V, 100 MHz. The measurement result shows energy efficiency of 0.6 fJ/bit/search and 8% improvement of figure-of-merit (FoM) (energy/bit/search) compared with the state-of-the-art works. ",

keywords = "Adaptive sensing, content addressable memory (CAM), memory, reference voltage, sensing margin, ternary CAM (TCAM)",

author = "Kyeongho Lee and Woong Choi and Jongsun Park",

note = "Funding Information: Manuscript received September 4, 2020; revised November 5, 2020; accepted November 25, 2020. Date of publication December 24, 2020; date of current version July 23, 2021. This article was approved by Associate Editor Vivek De. This work was supported in part by the National Research Foundation of Korea Grant funded by the Korea Government under Grant NRF-2020R1A2C3014820 and Grant NRF-2015M3D1A1070465; in part by Institute for Information & Communications Technology Promotion (IITP) Grant funded by the Korea Government (MSIP) under Grant 2020-0-01077; in part by the Development of Intelligent SoC having Multimodal IOT Interface for Data Sensing, Edge Computing Analysis and Data Sharing; in part by the Next Generation Semiconductor Research and Development Program funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) under Grant 20009972; in part by Sookmyung Women{\textquoteright}s University Research Grants under Grant 1-1903-2007; and in part by Samsung Electronics Co., Ltd. (Corresponding author: Woong Choi.) Kyeongho Lee and Jongsun Park are with the School of Electrical Engineering, Korea University, Seoul 136-713, South Korea. Funding Information: This work was supported in part by the National Research Foundation of Korea Grant funded by the Korea Government under Grant NRF-2020R1A2C3014820 and Grant NRF-2015M3D1A1070465; in part by Institute for Information & Communications Technology Promotion (IITP) Grant funded by the Korea Government (MSIP) under Grant 2020-0-01077; in part by the Development of Intelligent SoC having Multimodal IOT Interface for Data Sensing, Edge Computing Analysis and Data Sharing; in part by the Next Generation Semiconductor Research and Development Program funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) under Grant 20009972; in part by Sookmyung Women{\textquoteright}s University Research Grants under Grant 1-1903-2007; and in part by Samsung Electronics Co., Ltd. Publisher Copyright: {\textcopyright} 1966-2012 IEEE.",

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AB - This article presents an adaptive match-line (ML) discharge scheme for low-power, high-performance, and compact ternary content addressable memory (TCAM). In the proposed TCAM, the transposed cell topology enables the selectively controlled ML pull-down path and compact array area. By employing the adaptive ML discharge and ML boosting scheme, unnecessary ML discharge and redundant search-line (SL) switching are eliminated for low-cost TCAM search operation. In order to minimize ML voltage swing at a wide voltage range, a timing calibration scheme is also adopted in the proposed TCAM. A 128 $\times $ 64 test chip implemented with 65-nm CMOS technology shows that the proposed adaptive ML discharge improves up to 69% of search delay and saves 37% of search energy compared with the conventional approach at 1.1 V, 100 MHz. The measurement result shows energy efficiency of 0.6 fJ/bit/search and 8% improvement of figure-of-merit (FoM) (energy/bit/search) compared with the state-of-the-art works.

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A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

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