A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC

Dongsuk Shin; Janghoon Song; Hyunsoo Chae; Chulwoo Kim

doi:10.1109/JSSC.2009.2021447

A 7 ps jitter 0.053 mm² fast lock all-digital DLL with a wide range and high resolution DCC

Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

61 Citations (Scopus)

Abstract

This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

Original language	English
Article number	5226752
Pages (from-to)	2437-2451
Number of pages	15
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2009.2021447
Publication status	Published - 2009 Sept

Bibliographical note

Funding Information:
Manuscript received October 02, 2007; revised June 02, 2008. Current version published August 26, 2009. This work was supported by Hynix Semiconductor Inc. and in part by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea government (MEST) (No. R0A-2007-000-20059-0). D. Shin is with Hynix Semiconductor, Icheon, Kyunggi-Do 467-701, Korea. J. Song is with Samsung Electronics, Hwasung, Kyunggi-Do 445-701, Korea. H. Chae was with the Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea, and is now with Samsung Electronics Company, Ltd., Hwasung, Kyunggi-Do 445-701, Korea. C. Kim is with the Department of Electronics and Electrical Engineering, Korea University, Seoul 136-713, Korea (e-mail: ckim@korea.ac.kr). Digital Object Identifier 10.1109/JSSC.2009.2021447

Copyright:
Copyright 2009 Elsevier B.V., All rights reserved.

Keywords

Delay-locked loop (DLL)
Duty cycle corrector (DCC)
Fine code generator
Range doubler
Time-to-digital converter (TDC)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2009.2021447

Cite this

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title = "A 7 ps jitter 0.053 mm2 fast lock all-digital DLL with a wide range and high resolution DCC",

abstract = "This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.",

keywords = "Delay-locked loop (DLL), Duty cycle corrector (DCC), Fine code generator, Range doubler, Time-to-digital converter (TDC)",

author = "Dongsuk Shin and Janghoon Song and Hyunsoo Chae and Chulwoo Kim",

note = "Funding Information: Manuscript received October 02, 2007; revised June 02, 2008. Current version published August 26, 2009. This work was supported by Hynix Semiconductor Inc. and in part by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea government (MEST) (No. R0A-2007-000-20059-0). D. Shin is with Hynix Semiconductor, Icheon, Kyunggi-Do 467-701, Korea. J. Song is with Samsung Electronics, Hwasung, Kyunggi-Do 445-701, Korea. H. Chae was with the Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea, and is now with Samsung Electronics Company, Ltd., Hwasung, Kyunggi-Do 445-701, Korea. C. Kim is with the Department of Electronics and Electrical Engineering, Korea University, Seoul 136-713, Korea (e-mail: ckim@korea.ac.kr). Digital Object Identifier 10.1109/JSSC.2009.2021447 Copyright: Copyright 2009 Elsevier B.V., All rights reserved.",

year = "2009",

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N1 - Funding Information: Manuscript received October 02, 2007; revised June 02, 2008. Current version published August 26, 2009. This work was supported by Hynix Semiconductor Inc. and in part by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea government (MEST) (No. R0A-2007-000-20059-0). D. Shin is with Hynix Semiconductor, Icheon, Kyunggi-Do 467-701, Korea. J. Song is with Samsung Electronics, Hwasung, Kyunggi-Do 445-701, Korea. H. Chae was with the Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea, and is now with Samsung Electronics Company, Ltd., Hwasung, Kyunggi-Do 445-701, Korea. C. Kim is with the Department of Electronics and Electrical Engineering, Korea University, Seoul 136-713, Korea (e-mail: ckim@korea.ac.kr). Digital Object Identifier 10.1109/JSSC.2009.2021447 Copyright: Copyright 2009 Elsevier B.V., All rights reserved.

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N2 - This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

AB - This paper presents a fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all-digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes. The ADDLL uses a self-calibration scheme to reduce the phase error and jitter, and a range doubler to double its operating frequency range with a negligible increase in power and area. The ADDCC employs a weighted signal generator to improve a resolution problem at high operating frequencies and a cycle detector to insure a wide operation range. The proposed ADDLL with the ADDCC was fabricated using a 0.18 μ m CMOS technology that operates over a wide frequency range from 440 MHz to 1.5 GHz with 15 cycles of maximum lock time. The peak-to-peak jitter is 7∼ps at 1.5 GHz with a power consumption of 43 mW and the area is 0.053 mm2.

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KW - Range doubler

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